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IS-80C52 の電気的特性と機能

IS-80C52のメーカーはIntegrated Silicon Solutionです、この部品の機能は「(IS-80C32 / IS-80C52) CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS-80C52
部品説明 (IS-80C32 / IS-80C52) CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER
メーカ Integrated Silicon Solution
ロゴ Integrated Silicon Solution ロゴ 




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IS-80C52 Datasheet, IS-80C52 PDF,ピン配置, 機能
IIISSS88008CC05322C52
IS80C32
CMOS SINGLE CHIP
LOW VOLTAGE
8-BIT MICROCONTROLLER
FEATURES
• 80C51 based architecture
• 8K x 8 ROM (IS80C52 only)
• 256 x 8 RAM
www.DataSheet4TUh.croeme 16-bit Timer/Counters
• Full duplex serial channel
• Boolean processor
• Four 8-bit I/O ports, 32 I/O lines
• Memory addressing capability
– 64K ROM and 64K RAM
• Program memory lock
– Encrypted verify (32 bytes)
– Lock bits (2)
• Power save modes:
– Idle and power-down
• Eight interrupt sources
• Most instructions execute in 0.3 µs
• CMOS and TTL compatible
• Maximum speed: 40 MHz @ Vcc = 5V
• Industrial temperature available
• Packages available:
– 40-pin DIP
– 44-pin PLCC
– 44-pin PQFP
ISSISISI®®
NOVEMBER 1998
GENERAL DESCRIPTION
The ISSI IS80C52 and IS80C32 are high-performance
microcontrollers fabricated using high-density CMOS
technology. The CMOS IS80C52/32 is functionally
compatible with the industry standard 8052/32
microcontrollers.
The IS80C52/32 is designed with 8K x 8 ROM (IS80C52
only); 256 x 8 RAM; 32 programmable I/O lines; a serial
I/O port for either multiprocessor communications, I/O
expansion or full duplex UART; three 16-bit timer/counters;
an eight-source, two-priority-level, nested interrupt
structure; and an on-chip oscillator and clock circuit. The
IS80C52/32 can be expanded using standard TTL
compatible memory.
T2/P1.0
T2EX/P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RxD/P3.0
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
WR/P3.6
RD/P3.7
XTAL2
XTAL1
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VCC
39 P0.0/AD0
38 P0.1/AD1
37 P0.2/AD2
36 P0.3/AD3
35 P0.4/AD4
34 P0.5/AD5
33 P0.6/AD6
32 P0.7/AD7
31 EA
30 ALE
29 PSEN
28 P2.7/A15
27 P2.6/A14
26 P2.5/A13
25 P2.4/A12
24 P2.3/A11
23 P2.2/A10
22 P2.1/A9
21 P2.0/A8
Figure 1. IS80C52/32 Pin Configuration:
40-pin PDIP
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 1998, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC004-1D
11/19/98
1

1 Page





IS-80C52 pdf, ピン配列
IS80C52
IS80C32
ISSI ®
P1.5
www.DataSheet4U.com
P1.6
P1.7
RST
RxD/P3.0
NC
TxD/P3.1
INT0/P3.2
INT1/P3.3
T0/P3.4
T1/P3.5
44 43 42 41 40 39 38 37 36 35 34
1 33
2 32
3 31
4 30
5 29
6 29
7 27
8 26
9 25
10 24
11 23
12 13 14 15 16 17 18 19 20 21 22
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NC
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
Figure 3. IS80C52/32 Pin Configuration: 44-pin PQFP
Integrated Silicon Solution, Inc. — 1-800-379-4774
MC004-1D
11/19/98
3


3Pages


IS-80C52 電子部品, 半導体
IS80C52
IS80C32
Table 1. Detailed Pin Description (continued)
Symbol PDIP
P3.0-P3.7 10-17
PLCC
PQFP I/O
11, 13-19 5, 7-13 I/O
10 11
5I
11 13
7O
www.DataSheet4U.com
12
14
8I
13 15
9I
14 16 10 I
15 17 11 I
16 18 12 O
17 19 13 O
PSEN
29 32 26 O
RST
9 10 4 I
XTAL 1
19
21
15 I
XTAL 2
18
20
14 O
GND 20 22 16 I
Vcc 40 44 38 I
ISSI ®
Name and Function
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal
pullups. Port 3 pins that have 1s written to them are pulled high
by the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally pulled low will source current
because of the internal pullups. (See DC Characteristics: IIL).
Port 3 also serves the special features of the IS80C51/31, as
listed below:
RxD (P3.0): Serial input port.
TxD (P3.1): Serial output port.
INT0 (P3.2): External interrupt 0.
INT1 (P3.3): External interrupt 1.
T0 (P3.4): Timer 0 external input.
T1 (P3.5): Timer 1 external input.
WR (P3.6): External data memory write strobe.
RD (P3.7): External data memory read strobe.
Program Store Enable: The read strobe to external program
memory. When the device is executing code from the external
program memory, PSEN is activated twice each machine
cycle except that two PSEN activations are skipped during
each access to external data memory. PSEN is not activated
during fetches from internal program memory.
Reset: A high on this pin for two machine cycles while the
oscillator is running, resets the device. An internal MOS
resistor to GND permits a power-on reset using only an
external capacitor connected to Vcc.
Crystal 1: Input to the inverting oscillator amplifier and
input to the internal clock generator circuits.
Crystal 2: Output from the inverting oscillator amplifier.
Ground: 0V reference.
Power Supply: This is the power supply voltage for operation.
6 Integrated Silicon Solution, Inc. — 1-800-379-4774
MC004-1D
11/19/98

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
IS-80C52

(IS-80C32 / IS-80C52) CMOS SINGLE CHIP LOW VOLTAGE 8-BIT MICROCONTROLLER

Integrated Silicon Solution
Integrated Silicon Solution


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