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CY14E256L の電気的特性と機能

CY14E256LのメーカーはCypress Semiconductorです、この部品の機能は「256-Kbit (32K x 8) nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14E256L
部品説明 256-Kbit (32K x 8) nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY14E256L Datasheet, CY14E256L PDF,ピン配置, 機能
PRELIMINARY
CY14E256L
256-Kbit (32K x 8) nvSRAM
Features
• 25 ns and 45 ns Access Times
• “Hands-off” Automatic STORE on Power Down with
external 68µF capacitor
STORE to QuantumTrap® Nonvolatile Elements is
initiated by Software, Hardware or Autostore® on
www.DataSheet4UP.coowmer-down
RECALL to SRAM Initiated by Software or Power-up
• Infinite READ, WRITE and RECALL Cycles
• 15 mA Typical ICC at 200 ns Cycle Time
• 1,000,000 STORE Cycles to QuantumTrap
• 100-Year Data Retention to QuantumTrap
• Single 5V Operation +10%
• Commercial Temperature
• SOIC Package
• RoHS Compliance
Functional Description
The Cypress CY14E256L is a fast static RAM with a nonvol-
atile element in each memory cell. The embedded nonvolatile
elements incorporate QuantumTrap technology producing the
world’s most reliable nonvolatile memory. The SRAM provides
Infinite read and write cycles, while independent, nonvolatile
data resides in the highly reliable QuantumTrap cell. Data
transfers from the SRAM to the nonvolatile elements (the
STORE operation) takes place automatically at power down.
On power-up, data is restored to the SRAM (the RECALL
operation) from the nonvolatile memory. Both the STORE and
RECALL operations are also available under software control.
A hardware STORE may be initiated with HSB pin.
Logic Block Diagram
Quantum Trap
VCC
VCAP
512 X 512
A5
STORE
POWER
CONTROL
A6
A7
A8
A9
A 11
A 12
STATIC RAM
ARRAY
512 X 512
RECALL
STORE/
RECALL
CONTROL
HSB
A 13
A14 SOFTWARE
-DETECT
A13 A0
DQ 0
DQ 1
DQ 2
DQ 3
DQ 4
DQ 5
DQ 6
DQ 7
COLUMN I/O
COLUMN DEC
A0 A1 A2 A3 A4 A10
OE
CE
WE
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709
• 408-943-2600
Document #: 001-06968 Rev. *C
Revised November 28, 2006
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CY14E256L pdf, ピン配列
PRELIMINARY
CY14E256L
Device Operation
The CY14E256L nvSRAM is made up of two functional
components paired in the same physical cell. These are a
SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM.
Data in the SRAM can be transferred to the nonvolatile cell
(the STORE operation), or from the nonvolatile cell to SRAM
(the RECALL operation). This unique architecture allows all
cells to be stored and recalled in parallel. During the STORE
and RECALL operations SRAM READ and WRITE operations
are inhibited. The CY14E256L supports Infinite reads and
writes just like a typical SRAM. In addition, it provides Infinite
RECALL operations from the nonvolatile cells and up to
www.DataSheet14Um.cilolimon STORE operations.
SRAM Read
The CY14E256L performs a READ cycle whenever CE and
OE are low while WE and HSB are high. The address specified
on pins A0–14 determines which of the 32,768 data bytes will
be accessed. When the READ is initiated by an address
transition, the outputs will be valid after a delay of tAA (READ
cycle #1). If the READ is initiated by CE or OE, the outputs will
be valid at tACE or at tDOE, whichever is later (READ cycle #2).
The data outputs will repeatedly respond to address changes
within the tAA access time without the need for transitions on
any control input pins, and will remain valid until another
address change or until CE or OE is brought high, or WE or
HSB is brought low.
SRAM Write
A WRITE cycle is performed whenever CE and WE are low
and HSB is high. The address inputs must be stable prior to
entering the WRITE cycle and must remain stable until either
CE or WE goes high at the end of the cycle. The data on the
common I/O pins I/O0–7 will be written into the memory if it is
valid tSD before the end of a WE controlled WRITE or before
the end of an CE controlled WRITE. It is recommended that
OE be kept high during the entire WRITE cycle to avoid data
bus contention on common I/O lines. If OE is left low, internal
circuitry will turn off the output buffers tHZWE after WE goes
low.
AutoStore Operation
The CY14E256L stores data to nvSRAM using one of three
storage operations. These three operations are Hardware
Store, activated by HSB, Software Store, activated by an
address sequence, and AutoStore, on device power down.
AutoStore operation is a unique feature of QuantumTrap
technology and is enabled by default on the CY14E256L.
During normal operation, the device will draw current from VCC
to charge a capacitor connected to the VCAP pin. This stored
charge will be used by the chip to perform a single STORE
operation. If the voltage on the VCC pin drops below VSWITCH,
the part will automatically disconnect the VCAP pin from VCC.
A STORE operation will be initiated with power provided by the
VCAP capacitor.
Figure 1 shows the proper connection of the storage capacitor
(VCAP) for automatic store operation. Refer to the DC Charac-
teristics table for the size of VCAP. The voltage on the VCAP pin
is driven to 5V by a charge pump internal to the chip. A pull-up
should be placed on WE to hold it inactive during power-up.
Figure 1. AutoStore® Mode
Figure 2. System Power Mode
Document #: 001-06968 Rev. *C
Page 3 of 16
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CY14E256L 電子部品, 半導体
PRELIMINARY
CY14E256L
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage on VCC Relative to GND.......... –0.5V to 7.0V
Voltage Applied to Outputs
in High-Z State .......................................–0.5V to VCC + 0.5V
Input Voltage ............................................ –0.5V to Vcc+0.5V
Transient Voltage (<20 ns) on
www.DataSheetA4nUy.cPomin to Ground Potential...................–2.0V to VCC + 2.0V
Package Power Dissipation
Capability (TA = 25°C) ................................................... 1.0W
Surface Mount Lead Soldering
Temperature (3 Seconds) .......................................... +260°C
Output Short Circuit Current [1].................................... 15 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Range Ambient Temperature
Commercial
0°C to +70°C
VCC
4.5V to 5.5V
DC Electrical Characteristics Over the Operating Range (VCC = 4.5V to 5.5V) [2]
Parameter
Description
Test Conditions
Min. Max. Unit
ICC1
Average VCC Current tRC = 25 ns
Commercial
tRC = 45 ns
Dependent on output loading and cycle rate.
Values obtained without output loads. IOUT = 0mA.
ICC2 Average VCC Current All Inputs Don’t Care, VCC = Max.
during STORE
Average current for duration tSTORE
ICC3 Average VCC Current at WE > (VCC – 0.2). All other inputs cycling.
tAVAV = 200 ns, 5V,
Dependent on output loading and cycle rate. Values obtained
25°C typical
without output loads.
97 mA
70 mA
mA
3 mA
15 mA
ICC4 Average VCAP Current All Inputs Don’t Care, VCC = Max.
during AutoStore Cycle Average current for duration tSTORE
ISB VCC Standby Current CE > (VCC – 0.2). All others VIN < 0.2V or > (VCC – 0.2V).
Standby current level after nonvolatile cycle is complete.
Inputs are static. f = 0MHz.
2 mA
1.5 mA
IIX Input Leakage Current VCC = Max., VSS < VIN < VCC
IOZ
Off-State Output
VCC = Max., VSS < VIN < VCC,
Leakage Current
CE or OE > VIH
VIH Input HIGH Voltage
VIL Input LOW Voltage
VOH Output HIGH Voltage IOUT = –2 mA
VOL Output LOW Voltage IOUT = 4 mA
-1 +1 µA
-5 +5 µA
2.2 VCC + 0.5
VSS – 0.5 0.8
2.4
0.4
V
V
V
V
Capacitance [3]
Parameter
Description
Test Conditions
Max.
Unit
CIN
COUT
Input Capacitance
Output Capacitance
TA = 25°C, f = 1 MHz,
VCC = 0 to 3.0V
5 pF
7 pF
Notes:
1. Outputs shorted for no more than one second. No more than one output shorted at a time.
2. Typical conditions for the Active Current shown on the front page of the data sheet are average values at 25°C (room temperature), and VCC = 5V. Not 100% tested.
3. These parameters are guaranteed but not tested.
Document #: 001-06968 Rev. *C
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