PDF CY14B101K Data sheet ( Hoja de datos )

Número de pieza	CY14B101K
Descripción	1 Mbit (128K x 8) nvSRAM
Fabricantes	Cypress Semiconductor
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No Preview Available ! PRELIMINARY CY14B101K 1 Mbit (128K x 8) nvSRAM With Real-Time Clock Features • Data integrity of Cypress nvSRAM combined with full featured Real-Time Clock (RTC) • Watchdog timer • Clock alarm with programmable interrupts • Capacitor or battery backup for RTC www.DataSheet4•U2.c5onms, 35 ns, and 45 ns access times • “Hands-off” automatic STORE on power down with only a small capacitor • STORE to QuantumTrap™ initiated by software, device pin, or on power down • RECALL to SRAM initiated by software or on power up • Infinite READ, WRITE, and RECALL cycles • High reliability — Endurance to 200,000 cycles — Data retention: 20 years @55°C • 10 mA typical ICC at 200 ns cycle time • Single 3V operation +20%, –10% • Commercial and industrial temperature • SSOP package (ROHS compliant) Logic Block Diagram Functional Description The Cypress CY14B101K combines a 1 Mbit nonvolatile static RAM with a full featured real-time clock in a monolithic integrated circuit. The embedded nonvolatile elements incorporate QuantumTrap technology producing the world’s most reliable nonvolatile memory. The SRAM can be read and written an infinite number of times, while independent, nonvolatile data resides in the nonvolatile elements. The Real-Time Clock function provides an accurate clock with leap year tracking and a programmable, high accuracy oscillator. The alarm function is programmable for one time alarm or periodic seconds, minutes, hours, or days. There is also a programmable watchdog timer for process control. A5 A6 A7 A8 A9 A 12 A 13 A 14 A 15 A 16 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 QuantumTrap 1024 x 1024 STORE STATIC RAM ARRAY 1024 X 1024 RECALL COLUMN IO COLUMN DEC A 0 A1 A 2 A 3 A 4 A 10 A 11 VCC VCAP POWER CONTROL STORE/ RECALL CONTROL VRTCbat VRTCcap HSB SOFTWARE DETECT -A15 A0 RTC MUX x1 x2 INT -A16 A0 OE CE WE Cypress Semiconductor Corporation Document #: 001-06401 Rev. E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 01, 2007 [+] Feedback 1 page Table 1. Mode Selection CE WE HX LH LL LH www.DataSheet4U.com L H LH LH PRELIMINARY CY14B101K OE A15 – A0 Mode IO Power X X Not Selected Output High-Z Standby L X READ SRAM Output Data Active X X WRITE SRAM Input Data Active L 0x4E38 READ SRAM Output Data Active[1, 2, 3] 0xB1C7 READ SRAM Output Data 0x83E0 READ SRAM Output Data 0x7C1F READ SRAM Output Data 0x703F READ SRAM Output Data 0x8B45 Autostore Output Data Disable L 0x4E38 READ SRAM Output Data Active[1, 2, 3] 0xB1C7 READ SRAM Output Data 0x83E0 READ SRAM Output Data 0x7C1F READ SRAM Output Data 0x703F Read SRAM Output Data 0x4B46 Autostore Output Data Enable L 0x4E38 Read SRAM Output Data Active ICC2[1, 2, 3] 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x8FC0 Nonvolatile Output High-Z Store L 0x4E38 Read SRAM Output Data Active[1, 2, 3] 0xB1C7 Read SRAM Output Data 0x83E0 Read SRAM Output Data 0x7C1F Read SRAM Output Data 0x703F Read SRAM Output Data 0x4C63 Nonvolatile Output High-Z Recall Notes 1. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle. 2. While there are 17 address lines on the CY14B101K, only the lower 16 lines are used to control software modes. 3. IO state depends on the state of OE. The IO table shown is based on OE Low. Document #: 001-06401 Rev. E Page 5 of 24 [+] Feedback 5 Page PRELIMINARY CY14B101K Table 4. Register Map Detail (continued) Time Keeping – Hours 0x1FFFB D7 12/24 D6 0 D5 D4 10s Hours D3 D2 D1 Hours D0 Contains the BCD value of hours in 24 hour format. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 2. The range for the register is 0 – 23. Time Keeping – Minutes 0x1FFFA D7 0 D6 D5 D4 10s Minutes D3 D2 D1 Minutes D0 www.DataSheet4U.com Contains the BCD value of minutes. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper minutes digit and operates from 0 to 5. The range for the register is 0 – 59. Time Keeping – Seconds 0x1FFF9 D7 0 D6 D5 D4 10s Seconds D3 D2 D1 Seconds D0 Contains the BCD value of seconds. Lower nibble contains the lower digit and operates from 0 to 9; upper nibble contains the upper digit and operates from 0 to 5. The range for the register is 0 – 59. Calibration/Control 0X1FFF8 D7 OSCEN D6 D5 0 Calibration Sign D4 D3 D2 D1 Calibration D0 OSCEN Oscillator Enable. When set to 1, the oscillator is halted. When set to 0, the oscillator runs. Disabling the oscillator saves battery/capacitor power during storage. On a no battery power up, this bit is set to 0. Calibration Determines if the calibration adjustment is applied as an addition to or as a subtraction from the time base. Sign Calibration These five bits control the calibration of the clock. WatchDog Timer 0x1FFF7 D7 D6 D5 D4 D3 D2 D1 D0 WDS WDW WDT WDS Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to 0 has no affect. The bit is cleared automatically once the watchdog timer is reset. The WDS bit is WRITE only. Reading it always returns a 0. WDW Watchdog Write Enable. Setting this bit to 1 masks the watchdog timeout value (WDT5–WDT0) so it cannot be written. This allows the user to strobe the watchdog without disturbing the timeout value. Setting this bit to 0 allows bits 5 – 0 to be written on the next WRITE to the watchdog register. The new value will be loaded on the next internal watchdog clock after the WRITE cycle is complete. This function is explained in more detail in the watchdog timer section. WDT Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this register. It represents a multiplier of the 32 Hz count (31.25 ms). The minimum range or timeout value is 31.25 ms (a setting of 1) and the maximum timeout is 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0 disables the timer. These bits can be written only if the WDW bit was cleared to 0 on a previous cycle. Document #: 001-06401 Rev. *E Page 11 of 24 [+] Feedback 11 Page

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