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PDF 27SF512 Data sheet ( Hoja de datos )
| Número de pieza | 27SF512 | |
| Descripción | SST27SF512 | |
| Fabricantes | SST | |
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256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit (x8)
Many-Time Programmable Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
SST27SF256 / 512 / 010 / 0205.0V-Read 256Kb / 512Kb / 1Mb / 2Mb (x8) MTP flash memories
FEATURES:
Data Sheet
• Organized as 32K x8 / 64K x8 / 128K x8 / 256K x8
• 4.5-5.5V Read Operation
• Superior Reliability
– Endurance: At least 1000 Cycles
– Greater than 100 years Data Retention
• Low Power Consumption
– Active Current: 20 mA (typical)
– Standby Current: 10 µA (typical)
www.DataShee•t4UF.caosmt Read Access Time
– 70 ns
– 90 ns
• Fast Byte-Program Operation
– Byte-Program Time: 20 µs (typical)
– Chip Program Time:
0.7 seconds (typical) for SST27SF256
1.4 seconds (typical) for SST27SF512
2.8 seconds (typical) for SST27SF010
5.6 seconds (typical) for SST27SF020
• Electrical Erase Using Programmer
– Does not require UV source
– Chip-Erase Time: 100 ms (typical)
• TTL I/O Compatibility
• JEDEC Standard Byte-wide EPROM Pinouts
• Packages Available
– 32-pin PLCC
– 32-pin TSOP (8mm x 14mm)
– 28-pin PDIP for SST27SF256/512
– 32-pin PDIP for SST27SF010/020
PRODUCT DESCRIPTION
The SST27SF256/512/010/020 are a 32K x8 / 64K x8 /
128K x8 / 256K x8 CMOS, Many-Time Programmable
(MTP) low cost flash, manufactured with SST’s proprietary,
high performance SuperFlash technology. The split-gate
cell design and thick oxide tunneling injector attain better
reliability and manufacturability compared with alternate
approaches. These MTP devices can be electrically erased
and programmed at least 1000 times using an external pro-
grammer with a 12 volt power supply. They have to be
erased prior to programming. These devices conform to
JEDEC standard pinouts for byte-wide memories.
Featuring high performance Byte-Program, the
SST27SF256/512/010/020 provide a Byte-Program time of
20 µs. Designed, manufactured, and tested for a wide
spectrum of applications, these devices are offered with an
endurance of at least 1000 cycles. Data retention is rated at
greater than 100 years.
The SST27SF256/512/010/020 are suited for applications
that require infrequent writes and low power nonvolatile
storage. These devices will improve flexibility, efficiency,
and performance while matching the low cost in nonvolatile
applications that currently use UV-EPROMs, OTPs, and
mask ROMs.
To meet surface mount and conventional through hole
requirements, the SST27SF256/512 are offered in 32-pin
PLCC, 32-pin TSOP, and 28-pin PDIP packages. The
SST27SF010/020 are offered in 32-pin PDIP, 32-pin PLCC
and 32-pin TSOP packages. See Figures 1, 2, and 3 for
pinouts.
©2001 Silicon Storage Technology, Inc.
S71152-02-000 5/01
502
1
Device Operation
The SST27SF256/512/010/020 are a low cost flash solu-
tion that can be used to replace existing UV-EPROM, OTP,
and mask ROM sockets. These devices are functionally
(read and program) and pin compatible with industry stan-
dard EPROM products. In addition to EPROM functionality,
these devices also support electrical erase operation via an
external programmer. They do not require a UV source to
erase, and therefore the packages do not have a window.
Read
The Read operation of the SST27SF256/512/010/020 is
controlled by CE# and OE#. Both CE# and OE# have to be
low for the system to obtain data from the outputs. Once
the address is stable, the address access time is equal to
the delay from CE# to output (TCE). Data is available at the
output after a delay of TOE from the falling edge of OE#,
assuming that CE# pin has been low and the addresses
have been stable for at least TCE - TOE. When the CE# pin
is high, the chip is deselected and a typical standby current
of 10 µA is consumed. OE# is the output control and is
used to gate data from the output pins. The data bus is in
high impedance state when either CE# or OE# is high.
Byte-Program Operation
The SST27SF256/512/010/020 are programmed by using
an external programmer. The programming mode for
SST27SF256/010/020 is activated by asserting 12V (±5%)
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
MTP is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
1 page  
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
SST27SF020 SST27SF010 SST27SF512 SST27SF256
A11
A9
A8
A13
A14
A17
PGM#
VDD
VPP
A16
A15
A12
www.DataSheet4U.coAAm76
A5
A4
A11
A9
A8
A13
A14
NC
PGM#
VDD
VPP
A16
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
NC
VDD
NC
NC
A15
A12
A7
A6
A5
A4
A11
A9
A8
A13
A14
NC
NC
VDD
VPP
NC
NC
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
FIGURE 2: PIN ASSIGNMENTS FOR 32-PIN TSOP (8MM X 14MM)
SST27SF256 SST27SF512 SST27SF010 SST27SF020
32
OE#
OE#/VPP OE#
31 A10 A10
A10
30 CE# CE#
CE#
29
DQ7
DQ7
DQ7
28
DQ6
DQ6
DQ6
27
DQ5
DQ5
DQ5
26
DQ4
DQ4
DQ4
25
DQ3
DQ3
DQ3
24
VSS
VSS
23
DQ2
DQ2
VSS
DQ2
22
DQ1
DQ1
DQ1
21
DQ0
DQ0
DQ0
20 A0 A0
A0
19 A1 A1
A1
18 A2 A2
A2
17 A3 A3
A3
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
502 ILL F01.1
SST27SF512 SST27SF256
SST27SF256 SST27SF512
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VPP
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1 28
2 27
3 26
4 25
5 24
6 28-pin 23
7 PDIP 22
8 Top View 21
9 20
10 19
11 18
12 17
13 16
14 15
VDD
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
A14
A13
A8
A9
A11
OE#/VPP
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
502 ILL F02a.1
SST27SF020 SST27SF010
SST27SF010 SST27SF020
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
VPP
A16
A15
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
2
3
4
5
6 32-pin
7 PDIP
8 Top View
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VDD
PGM#
NC
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
VDD
PGM#
A17
A14
A13
A8
A9
A11
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
502 ILL F02b.1
FIGURE 3: PIN ASSIGNMENTS FOR 28-PIN AND 32-PIN PDIP
©2001 Silicon Storage Technology, Inc.
5
S71152-02-000 5/01 502
5 Page 
256 Kbit / 512 Kbit / 1 Mbit / 2 Mbit Multi-Purpose Flash
SST27SF256 / SST27SF512 / SST27SF010 / SST27SF020
Data Sheet
TABLE 14: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR SST27SF256
Symbol
TAS
TAH
TPRT
TVPS
TVPH
TPW
TEW
www.DataSheet4TUDS.com
TDH
TVR
TART
TA9S
TA9H
Parameter
Address Setup Time
Address Hold Time
VPP Pulse Rise Time
VPP Setup Time
VPP Hold Time
CE# Program Pulse Width
CE# Erase Pulse Width
Data Setup Time
Data Hold Time
VPP and A9 Recovery Time
A9 Rise Time to 12V during Erase
A9 Setup Time during Erase
A9 Hold Time during Erase
Min
1
1
50
1
1
20
100
1
1
1
50
1
1
TABLE 15: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR SST27SF512
Symbol
TAS
TAH
TPRT
TVPS
TVPH
TPW
TEW
TDS
TDH
TVR
TART
TA9S
TA9H
Parameter
Address Setup Time
Address Hold Time
OE#/VPP Pulse Rise Time
OE#/VPP Setup Time
OE#/VPP Hold Time
CE# Program Pulse Width
CE# Erase Pulse Width
Data Setup Time
Data Hold Time
OE#/VPP and A9 Recovery Time
A9 Rise Time to 12V during Erase
A9 Setup Time during Erase
A9 Hold Time during Erase
Min
1
1
50
1
1
20
100
1
1
1
50
1
1
TABLE 16: PROGRAM/ERASE CYCLE TIMING PARAMETERS FOR SST27SF010/020
Symbol
TCES
TCEH
TAS
TAH
TPRT
TVPS
TVPH
TPW
TEW
TDS
TDH
TVR
TART
TA9S
TA9H
Parameter
CE# Setup Time
CE# Hold Time
Address Setup Time
Address Hold Time
VPP Pulse Rise Time
VPP Setup Time
VPP Hold Time
PGM# Program Pulse Width
PGM# Erase Pulse Width
Data Setup Time
Data Hold Time
A9 Recovery Time for Erase
A9 Rise Time to 12V during Erase
A9 Setup Time during Erase
A9 Hold Time during Erase
Min
1
1
1
1
50
1
1
20
100
1
1
1
50
1
1
©2001 Silicon Storage Technology, Inc.
11
Max
30
500
Units
µs
µs
ns
µs
µs
µs
ms
µs
µs
µs
ns
µs
µs
T14.0 502
Max
30
500
Units
µs
µs
ns
µs
µs
µs
ms
µs
µs
µs
ns
µs
µs
T15.0 502
Max
30
500
Units
µs
µs
µs
µs
ns
µs
µs
µs
ms
µs
µs
µs
ns
µs
µs
T16.0 502
S71152-02-000 5/01 502
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet 27SF512.PDF ] | |
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