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PDF HT48CA3 Data sheet ( Hoja de datos )

Número de pieza HT48CA3
Descripción (HT48RA3 / HT48CA3) 8-Bit Remote Type OTP MCU
Fabricantes Holtek Semiconductor 
Logotipo Holtek Semiconductor Logotipo



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HT48RA3/HT48CA3
Remote Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
www.DataSheet4U.com
- HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
- HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
- HA0041E Using the HT48CA0 to Generate the HT6221 Output Signals
- HA0075E MCU Reset and Oscillator Circuits Application Note
- HA0076E HT48RAx/HT48CAx Software Application Note
- HA0082E HT48xA0-1 and HT48xA0-2 Power-on Reset Timing
Features
· Operating voltage: 2.0V~5.5V
· 23 bidirectional I/O lines (max.)
· 1 interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with overflow
interrupt and 8-stage prescaler (TMR0)
· 16-bit programmable timer/event counter and over-
flow interrupts (TMR1)
· On-chip crystal and RC oscillator
· Watchdog Timer
· 24K´16 program memory ROM (8K´16 bits´3
banks)
· 224´8 data memory RAM
· PFD supported
· HALT function and wake-up feature reduce power
consumption
· 8-level subroutine nesting
· Up to 1ms instruction cycle with 4MHz system clock at
VDD=3V
· Bit manipulation instruction
· 16-bit table read instruction
· 63 powerful instructions
· All instructions in one or two machine cycles
· Low voltage reset function
· 28-pin SOP/SSOP (209mil) package
General Description
The HT48RA3/HT48CA3 are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for multiple I/O control product applications.
The data ROM can be used to store remote control
codes. The mask version HT48CA3 is fully pin and func-
tionally compatible with the OTP version HT48RA3 de-
vice.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, watchdog timer,
programmable frequency divider, HALT and wake-up
functions, as well as low cost, enhance the versatility of
these devices to suit a wide range of application possi-
bilities such as industrial control, consumer products,
subsystem controllers, and particularly suitable for use
in products such as universal remote controller (URC).
Rev. 1.30
1 October 12, 2007

1 page




HT48CA3 pdf
HT48RA3/HT48CA3
A.C. Characteristics
Symbol
Parameter
Test Conditions
VDD Conditions
fSYS1
System Clock
(Crystal OSC)
¾ 2.0V~5.5V
¾ 3.3V~5.5V
fSYS2
System Clock
(RC OSC)
¾ 2.0V~5.5V
¾ 3.3V~5.5V
www.DataSheet4U.com
fTIMER
tWDTOSC
Timer I/P Frequency
(TMR0/TMR1)
Watchdog Oscillator Period
3V
50% duty
5V
3V
¾
5V
tWDT1
Watchdog Time-out Period
(WDT OSC)
3V
Without WDT prescaler
5V
tWDT2 Watchdog Time-out Period (fSYS/4) ¾ Without WDT prescaler
tRES
External Reset Low Pulse Width
¾
¾
tSST System Start-up Timer Period
¾
Power-up reset or
wake-up from HALT
tLVR Low Voltage Width to Reset
¾
¾
tINT Interrupt Pulse Width
¾¾
tACC Data ROM Access Time ¾ ¾
Note: tSYS=1/(fSYS)
Min.
400
400
400
400
0
0
45
32
11
8
¾
1
¾
1
1
1
Typ.
¾
¾
¾
¾
¾
¾
90
65
23
17
1024
¾
1024
¾
¾
¾
Ta=25°C
Max. Unit
4000
8000
4000
8000
4000
8000
180
130
46
33
¾
¾
¾
¾
¾
¾
kHz
kHz
kHz
kHz
kHz
kHz
ms
ms
ms
ms
tSYS
ms
tSYS
ms
ms
ms
Rev. 1.30
5 October 12, 2007

5 Page





HT48CA3 arduino
HT48RA3/HT48CA3
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator), instruction clock (system
clock divided by 4), determines the ROM code option.
This timer is designed to prevent a software malfunction
or sequence from jumping to an unknown location with
unpredictable results. The Watchdog Timer can be dis-
abled by ROM code option. If the Watchdog Timer is dis-
abled, all the executions related to the WDT result in no
operation.
Once the internal WDT oscillator (RC oscillator with a
period of 90ms at 3V normally) is selected, it is first di-
www.DataSheet4U.com vided by 256 (8-stage) to get the nominal time-out pe-
riod of 23ms at 3V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.9s/3V
seconds. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and oper-
ates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting pur-
pose. In this situation the logic can only be restarted by
external logic. The high nibble and bit 3 of the WDTS are
reserved for user¢s defined flags, which can be used to
indicate some specified status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recom-
mended, since the HALT will stop the system clock.
WS2 WS1 WS0
Division Ratio
000
001
010
011
100
101
110
111
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
WDTS Register
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset² and only
the program counter and SP are reset to zero. To clear
the contents of WDT (including the WDT prescaler),
three methods are adopted; external reset (a low level to
RES), software instruction and a ²HALT² instruction.
The software instruction include ²CLR WDT² and the
other set - ²CLR WDT1² and ²CLR WDT2². Of these
two types of instruction, only one can be active depend-
ing on the ROM code option - ²CLR WDT times selec-
tion option². If the ²CLR WDT² is selected (i.e. CLRWDT
times equal one), any execution of the ²CLR WDT² in-
struction will clear the WDT. In the case that ²CLR
WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT
times equal two), these two instructions must be exe-
cuted to clear the WDT; otherwise, the WDT may reset
the chip as a result of time-out.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
· The contents of the on chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
· All of the I/O ports maintain their original status.
· The PDF flag is set and the TO flag is cleared.
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge sig-
nal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow per-
forms a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or execut-
ing the ²CLR WDT² instruction and is set when execut-
ing the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the program counter and SP; the others remain in their
original status.
S y s te m C lo c k /4
W DT
O SC
ROM
C ode
O p tio n
S e le c t
8 - b it C o u n te r
W D T P r e s c a le r
7 - b it C o u n te r
8 -to -1 M U X
W S 0~W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 1.30
11 October 12, 2007

11 Page







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