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PDF HT48RA0-3 Data sheet ( Hoja de datos )
| Número de pieza | HT48RA0-3 | |
| Descripción | (HT48RA0-3 / HT48CA0-3) Remote Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT48RA0-3/HT48CA0-3
Remote Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
- HA0016E Writing and Reading to the HT24 EEPROM with the HT48 MCU Series
- HA0018E Controlling the HT1621 LCD Controller with the HT48 MCU Series
- HA0041E Using the HT48CA0 to Generate the HT6221 Output Signals
- HA0075E MCU Reset and Oscillator Circuits Application Note
- HA0076E HT48RAx/HT48CAx Software Application Note
www.DataSheet4U.com - HA0082E HT48xA0-1 and HT48xA0-2 Power-on Reset Timing
Features
· Operating voltage: fSYS=4MHz(±3%) at 2.0V~3.6V,
Temperature = 0°C ~ +50°C
· 10 bidirectional I/O lines
· 6 Schmitt trigger input lines
(PB7 without Pull-high resistor)
· One programmable carrier output - using 9-bit timer
· On-chip RC oscillator - 4MHz ±3% when
VDD=2.0V~3.6V; Temperature = 0°C ~ +50°C
· Watchdog Timer
· 1K´14 program memory
· 32´8 data RAM
· Power-down and wake-up features reduce power
consumption
· 62 powerful instructions
· Up to 1ms instruction cycle with 4MHz system clock
· All instructions executed in 1 or 2 machine cycles
· 14-bit table read instructions
· One-level subroutine nesting
· Bit manipulation instructions
· Low voltage reset function
· 20-pin SOP/SSOP package
General Description
The HT48RA0-3/HT48CA0-3 are 8-bit high perfor-
mance, RISC architecture microcontroller devices spe-
cifically designed for multiple I/O control product
applications. The mask version HT48CA0-3 is fully pin
and functionally compatible with the OTP version
HT48RA0-3 device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, watchdog timer, HALT and wake-up
functions, as well as low cost, enhance the versatility of
this device to suit a wide range of application possibili-
ties such as industrial control, consumer products, and
particularly suitable for use in products such as infrared
remote controllers and various subsystem controllers.
Rev.1.10
1 October 12, 2007
1 page  
HT48RA0-3/HT48CA0-3
The conditional skip is activated by instruction. Once the
condition is met, the next instruction, fetched during the
current instruction execution, is discarded and a dummy
cycle replaces it to get the proper instruction. Otherwise
proceed with the next instruction.
The lower byte of the program counter (PCL) is a read-
able and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
When a control transfer takes place, an additional
dummy cycle is required.
www.DataSheet4U.com Program Memory - ROM
The program memory is used to store the program in-
structions which are to be executed. It also contains
data and table and is organized into 1024´14 bits, ad-
dressed by the program counter and table pointer.
Certain locations in the program memory are reserved
for special usage:
· Location 000H
This area is reserved for the initialization program. Af-
ter a device reset, the program always begins execu-
tion at location 000H.
· Table location
Any location in the Program Memory space can be
used as a look-up table. The instructions TABRDC [m]
(the current page, one page=256 words) and TABRDL
[m] (the last page) transfer the contents of the
lower-order byte to the specified data memory
register, and the higher-order byte to TBLH (08H).
Only the destination of the lower-order byte in the ta-
000H
D e v ic e in itia liz a tio n p r o g r a m
n00H
L o o k - u p ta b le ( 2 5 6 w o r d s )
nFFH
P ro g ra m
L o o k - u p ta b le ( 2 5 6 w o r d s )
3FFH
1 4 b its
Program Memory
ble is well-defined, the other bits of the table word are
transferred to the lower portion of TBLH, the remain-
ing 2 bits are read as ²0². The Table Higher-order byte
register (TBLH) is read only. The table pointer (TBLP)
is a read/write register (07H), where P indicates the
table location. Before accessing the table, the location
must be placed in TBLP. The TBLH is read only and
cannot be restored. All table related instructions need
2 cycles to complete the operation. These areas may
function as normal program memory depending upon
the requirements.
Stack Register - STACK
This is a special part of the memory used to save the
contents of the program counter only. The stack is orga-
nized into one level and is neither part of the data nor
part of the program space, and is neither readable nor
writeable. The activated level is indexed by the stack
pointer and is neither readable nor writeable. At a sub-
routine call the contents of the program counter are
pushed onto the stack. At the end of a subroutine sig-
naled by a return instruction, RET, the program counter
is restored to its previous value from the stack. After a
chip reset, the SP will point to the top of the stack.
If the stack is full and a ²CALL² is subsequently exe-
cuted, stack overflow occurs and the first entry will be
lost and only the most recent return address is stored.
Data Memory - RAM
The data memory is divided into two functional groups:
special function registers and general purpose data
memory (32´8). Most are read/write, but some are read
only.
The remaining space before the 20H is reserved for fu-
ture expanded usage and reading these locations will
return the result 00H. The general purpose data mem-
ory, addressed from 20H to 3FH, is used for data and
control information under instruction command. All data
memory areas can handle arithmetic, logic, increment,
decrement and rotate operations directly. Except for some
dedicated bits, each bit in the data memory can be set and
reset by the SET [m].i and CLR [m].i instructions, respec-
tively. They are also indirectly accessible through memory
pointer register (MP;01H).
Instruction(s)
TABRDC [m]
TABRDL [m]
Table Location
*9 *8 *7 *6 *5 *4 *3 *2 *1 *0
P9 P8 @7 @6 @5 @4 @3 @2 @1 @0
1 1 @7 @6 @5 @4 @3 @2 @1 @0
Table Location
Note: *9~*0: Table location bits
P9~P8: Current program counter bits
@7~@0: Table pointer bits
Rev.1.10
5 October 12, 2007
5 Page 
HT48RA0-3/HT48CA0-3
· If the TSR1.1 is cleared during the timer counting, the
timer will be stopped. Once the TSR1.1 is set
(1®0®1), the down counter will reload data from
t8~t0, and then the down counter begins counting
down with the new load data.
· If TSR1.1 and TOEF are equal to 1 both, the timer can
re-start, after new data is written to TSR0, TSR1
(t0~t8) in sequence.
Note: If the contents of the Down counter is 000H, set
the t9 to start the timer counting, the timer will
only count 1 step. The timer output
time=64/fSYS. ® [ (0+1) ´ 64/fSYS=64/fSYS ]
www.DataSheet4U.com The down counter is decremented (-1) in the cycle of
64/fSYS. If the value of the down counter becomes ²0²,
the zero detector generates the timer operation end sig-
nal to stop the timer operation. At this time, TOEF will be
set to ²1². The output of the timer operation end signal is
continued while the down counter is ²0² and the timer is
stopped. The following relational expression applies be-
tween the timer¢s output time and the down counter¢s
set value.
Timer output time = (Set value+1) ´ 64/fSYS
An example is shown below.
MOV A,0FFH
MOV TSR0,A
MOV A,01H
MOV TSR1,A
SET TSR1.1
In the case above, the timer output time is as follows.
(Set value+1) ´ 64/fSYS
= (511+1) ´ 16ms
= 8.192ms
REM
8 .1 9 2 m s
By setting the flag (t9) that enables the timer output to
²1², the timer can output its operation status from the
REM pin. The REM pin can also output the carrier while
the timer is in operation.
Note:
The carrier output results if bit 9 of the high-level
period setting modulo register (CARH) is
cleared (²0²).
REM
T im e r O u tp u t T im e :
( S e t v a lu e + 1 ) x 6 4 /fS Y S
Timer Output when Carrier is not Output
tS R 1 tS R 0
t9 t8 t7 t6 t5 t4 t3 t2 t1 t0
D o w n C o u n te r, (t8 ~ t0 )+ 1
C ount
C lo c k
fS Y S /6 4
t9
C a r r ie r
S y n c h ro n o u s
C ir c u it
Z e ro D e te c to r
TO EF
R E M C a r r ie r S ig n a l
Timer Configuration
Rev.1.10
11 October 12, 2007
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet HT48RA0-3.PDF ] | |
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