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PDF HT48R50A-1 Data sheet ( Hoja de datos )
| Número de pieza | HT48R50A-1 | |
| Descripción | (HT48R50A-1 / HT48C50A-1) I/O Type 8-Bit MCU | |
| Fabricantes | Holtek Semiconductor | |
| Logotipo |  |
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HT48R50A-1/HT48C50-1
I/O Type 8-Bit MCU
Technical Document
· Tools Information
· FAQs
· Application Note
www.DataSheet4U.com
- HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM
- HA0004E HT48 & HT46 MCU UART Software Implementation Method
- HA0013E HT48 & HT46 LCM Interface Design
- HA0021E Using the I/O Ports on the HT48 MCU Series
- HA0055E 2^12 Decoder (8+4 - Corresponds to HT12E)
Features
· Operating voltage:
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
· Low voltage reset function
· 35 bidirectional I/O lines (max.)
· 1 interrupt input shared with an I/O line
· 8-bit programmable timer/event counter with overflow
interrupt and 8-stage prescaler
· 16-bit programmable timer/event counter and over-
flow interrupts
· On-chip RC oscillator, external crystal and RC oscil-
lator
· 32768Hz crystal oscillator for timing purposes only
· Watchdog Timer
· 4096´15 program memory ROM
· 160´8 data memory RAM
· Buzzer driving pair and PFD supported
· HALT function and wake-up feature reduce power
consumption
· 6-level subroutine nesting
· Up to 0.5ms instruction cycle with 8MHz system clock
at VDD=5V
· Bit manipulation instruction
· 15-bit table read instruction
· 63 powerful instructions
· All instructions in one or two machine cycles
· 28-pin SKDIP/SOP, 48-pin SSOP package
General Description
The HT48R50A-1/HT48C50-1 are 8-bit high perfor-
mance, RISC architecture microcontroller devices spe-
cifically designed for multiple I/O control product
applications. The mask version HT48C50-1 is fully pin
and functionally compatible with the OTP version
HT48R50A-1 device.
The advantages of low power consumption, I/O flexibil-
ity, timer functions, oscillator options, HALT and
wake-up functions, watchdog timer, buzzer driver, as
well as low cost, enhance the versatility of these devices
to suit a wide range of application possibilities such as
industrial control, consumer products, subsystem con-
trollers, etc.
Rev. 2.00
1 March 8, 2006
1 page  
HT48R50A-1/HT48C50-1
Symbol
Parameter
IOH I/O Port Source Current
RPH Pull-high Resistance
Test Conditions
VDD Conditions
3V VOH=0.9VDD
5V VOH=0.9VDD
3V ¾
5V ¾
Min.
-2
-5
20
10
Typ.
-4
-10
60
30
Max.
¾
¾
100
50
Unit
mA
mA
kW
kW
A.C. Characteristics
Symbol
www.DataSheet4U.com
Parameter
fSYS1 System Clock (Crystal OSC)
Test Conditions
VDD Conditions
¾ 2.2V~5.5V
¾ 3.3V~5.5V
fSYS2 System Clock (RC OSC)
¾ 2.2V~5.5V
¾ 3.3V~5.5V
3.2MHz
fSYS3
System Clock
(Internal RC OSC)
1.6MHz
5V
800kHz
400kHz
fTIMER Timer I/P Frequency (TMR)
¾ 2.2V~5.5V
¾ 3.3V~5.5V
tWDTOSC Watchdog Oscillator Period
3V
5V
¾
¾
tWDT1
Watchdog Time-out Period
(WDT OSC)
3V Without WDT
5V prescaler
tWDT2
Watchdog Time-out Period
(System Clock)
¾
Without WDT
prescaler
tWDT3
Watchdog Time-out Period
(RTC OSC)
¾
Without WDT
prescaler
tRES
External Reset Low Pulse
Width
¾
¾
tSST System Start-up Timer Period ¾ Wake-up from HALT
tINT Interrupt Pulse Width
¾
¾
Note: *tSYS= 1/fSYS1, 1/fSYS2 or 1/fSYS3
Min.
400
400
400
400
1800
900
450
225
0
0
45
32
11
8
¾
¾
1
¾
1
Typ.
¾
¾
¾
¾
¾
¾
¾
¾
¾
¾
90
65
23
17
1024
7.812
¾
1024
¾
Ta=25°C
Max.
4000
8000
4000
8000
5400
2700
1350
675
4000
8000
180
130
46
33
¾
Unit
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
kHz
ms
ms
ms
ms
*tSYS
¾ ms
¾ ms
¾ tSYS
¾ ms
Rev. 2.00
5 March 8, 2006
5 Page 
HT48R50A-1/HT48C50-1
OSC). Also, the frequencies of the internal RC oscillator
can be 3.2MHz, 1.6MHz, 800kHz and 400kHz (depends
on the options).
The WDT oscillator is a free running on-chip RC oscillator,
and no external components are required. Even if the sys-
tem enters the power down mode, the system clock is
stopped, but the WDT oscillator still works within a period
of 65ms at 5V. The WDT oscillator can be disabled by op-
tions to conserve power.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
www.DataSheet4U.com RC oscillator (WDT oscillator), RTC clock or instruction
clock (system clock divided by 4), determines the op-
tions. This timer is designed to prevent a software mal-
function or sequence from jumping to an unknown
location with unpredictable results. The Watchdog
Timer can be disabled by options. If the Watchdog Timer
is disabled, all the executions related to the WDT result
in no operation. The RTC clock is enabled only in the in-
ternal RC+RTC mode.
Once the internal WDT oscillator (RC oscillator with a
period of 65ms at 5V normally) is selected, it is first di-
vided by 256 (8-stage) to get the nominal time-out pe-
riod of 17ms at 5V. This time-out period may vary with
temperatures, VDD and process variations. By invoking
the WDT prescaler, longer time-out periods can be real-
ized. Writing data to WS2, WS1, WS0 (bit 2,1,0 of the
WDTS) can give different time-out periods. If WS2,
WS1, and WS0 are all equal to 1, the division ratio is up
to 1:128, and the maximum time-out period is 2.1s at 5V
seconds. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and oper-
ates in the same manner except that in the HALT state
the WDT may stop counting and lose its protecting pur-
pose. In this situation the logic can only be restarted by
external logic. The high nibble and bit 3 of the WDTS are
reserved for user's defined flags, which can be used to
indicate some specified status.
If the device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) or 32kHz crystal oscilla-
tor (RTC OSC) is strongly recommended, since the HALT
will stop the system clock.
WS2
0
0
0
0
1
1
1
1
WS1 WS0
Division Ratio
00
01
10
11
00
01
10
11
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
WDTS (09H) Register
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit ²TO². But in the HALT
mode, the overflow will initialize a ²warm reset² and only
the Program Counter and SP are reset to zero. To clear
the contents of WDT (including the WDT prescaler),
three methods are adopted; external reset (a low level to
RES), software instruction and a ²HALT² instruction.
The software instruction include ²CLR WDT² and the
other set - ²CLR WDT1² and ²CLR WDT2². Of these
two types of instruction, only one can be active depend-
ing on the option - ²CLR WDT times selection option². If
the ²CLR WDT² is selected (i.e. CLRWDT times equal
one), any execution of the ²CLR WDT² instruction will
clear the WDT. In the case that ²CLR WDT1² and ²CLR
WDT2² are chosen (i.e. CLRWDT times equal two),
these two instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip as a result
of time-out.
Power Down Operation - HALT
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
· The system oscillator will be turned off but the WDT
oscillator remains running (if the WDT oscillator is se-
lected).
· The contents of the on chip RAM and registers remain
unchanged.
· WDT and WDT prescaler will be cleared and re-
counted again (if the WDT clock is from the WDT os-
cillator).
S y s te m C lo c k /4
R TC O SC
W DT
O SC
O p tio n
S e le c t
8 - b it C o u n te r
W D T P r e s c a le r
7 - b it C o u n te r
8 -to -1 M U X
W S 0~W S 2
W D T T im e - o u t
Watchdog Timer
Rev. 2.00
11 March 8, 2006
11 Page | ||
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