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PDF PI2PCIE412-D Data sheet ( Hoja de datos )

Número de pieza PI2PCIE412-D
Descripción 2:1 Mux/DeMux Switch
Fabricantes Pericom Semiconductor 
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No Preview Available ! PI2PCIE412-D Hoja de datos, Descripción, Manual

PI2PCIE412-D
Enhanced, 1.8V, PCI Express Compliant,
4-Differential Channel, 2:1 Mux/DeMux Switch,
w/ Single Enable
Features
• 4 Differential Channel, 2:1 Mux/DeMux
• PCI Express signal compliance
• Low Bit-to-Bit Skew , 10ps max (between '+' and '-' bits)
• Low Crosstalk: -65dB@10 MHz
www.DataSheLeto4wU.cOofmf Isolation: -65dB@10 MHz
• VCC Operating Range: +1.5V to +2.0V
• ESD Tolerance: 8kV HBM I/O; 2kV HBM select pin
• Low channel-to-channel skew, 35ps max
• Packaging (Pb-free & Green):
– 42-contact, TQFN (ZH42)
Description
Pericom Semiconductor’s PI2PCIE412-D is an 8 to 4 differential
channel multiplexer/demultiplexer switch. This solution can
switch 2 full PCI Express lanes to one of two locations. Using
a unique design technique, Pericom has been able to minimize
the impedance of the switch such that the attenuation observed
through the switch is negligible. The unique design technique
also offers a layout targeted for PCI Express signals, which
minimizes the channel to channel skew as well as channel to
channel crosstalk as required by the PCI Express specification.
Application
Switch a PCI-Express lane output between two PCI Express lane
inputs.
Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
SEL
Truth Table
Function
AN to NB1
AN to NB2
0B1
1B1
2B1
3B1
0B2
1B2
2B2
3B2
4B1
5B1
6B1
7B1
4B2
5B2
6B2
7B2
SEL
L
H
Pin Description
GND
A0
A1
GND
VDD
A2
A3
VDD
SEL
GND
A4
A5
VDD
GND
A6
A7
GND
42 41 40 39
1 38
2 37
3 36
4 35
5 34
6 33
7 32
8 31
9 GND 30
10 29
11 28
12 27
13 26
14 25
15 24
16 23
17 22
18 19 20 21
0B1
1B1
2B1
3B1
0B2
1B2
2B2
3B2
VDD
4B1
5B1
6B1
7B1
4B2
5B2
6B2
7B2
1
PS8788B
01/23/06

1 page




PI2PCIE412-D pdf
PI2PCIE412-D
Enhanced, 1.8V, PCI Express Compliant,
4-Differential Channel, 2:1 Mux/DeMux Switch
Switching Characteristics (TA= -40º to +85ºC, VCC = 1.8V±10%)
Paramenter
Description
tPZH, tPZL Line Enable Time - SEL to AN, BN
tPHZ, tPLZ Line Disable Time - SEL to AN, BN
tb-b Bit-to-bit skew within the same differential pair
tch-ch
Channel-to-channel skew
www.DataSTheeestt4UC.ciormcuit for Electrical Characteristics(1-5)
VCC
Pulse
Generator
VIN
RT
D.U.T
VOUT
Min.
0.5
0.5
Max.
8.0
4.0
10
35
Units
ns
ps
ps
2 x VCC
200-ohm
4pF
CL
200-ohm
Notes:
1. CL = Load capacitance: includes jig and probe capacitance.
2. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator
3. Output 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
output 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
4. All input impulses are supplied by generators having the following characteristics: PRR ≤ MHz, ZO = 50Ω, tR ≤ 2.5ns, tF ≤ 2.5ns.
5. The outputs are measured one at a time with one transition per measurement.
Switching Waveforms
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Switch Positions
Test
tPLZ, tPZL (output on B-side)
tPHZ, tPZH (output on B-side)
Prop Delay
Voltage Waveforms Enable and Disable Times
Switch
2 x VCC
GND
Open
5
PS8788B
01/23/06

5 Page










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