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PDF U3741BM Data sheet ( Hoja de datos )
| Número de pieza | U3741BM | |
| Descripción | UHF ASK/FSK Receiver | |
| Fabricantes | TEMIC Semiconductors | |
| Logotipo |  |
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UHF ASK/FSK Receiver
U3741BM
Description
The U3741BM is a multi-chip PLL receiver device
supplied in an SO20 package. It has been specially
developed for the demands of RF low-cost data
transmission systems with low data rates from 1 kBaud to
10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manchester
or Bi-phase code. The receiver is well suited to operate
with the TEMIC PLL RF transmitter U2741B. Its main
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Features
D Minimal external circuitry requirements, no RF
components on the PC board except adaptation to the
receiver antenna
D High sensitivity, especially at low data rates
D Sensitivity reduction possible even while receiving
D Fully integrated VCO
D Low power consumption due to configurable self
polling with a programmable timeframe check
D Supply voltage 4.5 V to 5.5 V,
operating temperature range –40°C to 105°C
D Single-ended RF input for easy adaptation to
l/4 antenna or printed antenna on PCB
D Low-cost solution due to high integration level
applications are in the areas of telemetering, security
technology and keyless-entry systems. It can be used in
the frequency receiving range of f0 = 300 MHz to
450 MHz for ASK or FSK data transmission. All the
statements made below refer to 433.92-MHz and
315-MHz applications.
D ESD protection according to MIL-STD. 883
(4KV HBM) except Pin POUT (2KV HBM)
D High image frequency suppression due to 1 MHz IF
in conjunction with a SAW front-end filter. Up to
40 dB is thereby achievable with newer SAWs.
D Programmable output port for sensitivity selection or
for controlling external periphery
D Communication to m C possible via a single,
bi-directional data line
D Power management (polling) is also possible by
means of a separate pin via the m C
D 2 different IF bandwidth versions are available
(300 kHz and 600 kHz)
System Block Diagram
1 Li cell
Encoder
Keys M44Cx9x
UHF ASK/FSK
Remote control transmitter
U2741B
UHF ASK/FSK
Remote control receiver
U3741BM
Demod.
Control
XTO
PLL
VCO
Antenna Antenna
IF Amp
PLL
XTO
1...3
mC
Power
amp.
LNA
Figure 1. System block diagram
VCO
14917
Rev. A1, 15-Oct-98
Preliminary Information
1 (25)
1 page  
U3741BM
8 LNAGND
U3741BM
C3 L 9 LNA_N
22p 25n
8 LNAGND
U3741BM
C3 L 9 LNA_N
47p 25n
C16 C17
C16 C17
fRF = 433.92 MHz
100p
8.2p
L3
27n
TOKO LL2012
F27NJ
fRF = 315 MHz
100p
22p
L3
47n
TOKO LL2012
F47NJ
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RFIN
L2
TOKO LL2012
F33NJ
1 IN
B3555
OUT
C2 33n 2 IN_GND
OUT_GND
CASE_GND
8.2p 3,4 7,8
5
6
14105
RFIN
L2
TOKO LL2012
F82NJ
1 IN
B3551
OUT 5
C2 82n 2 IN_GND
OUT_GND 6
CASE_GND
10p 3,4 7,8
14106
Figure 5. Input matching network with SAW filter
fRF = 433.92 MHz
15p 25n
8 LNAGND
U3741BM
9 LNA_N
fRF = 315 MHz
33p 25n
8 LNAGND
U3741BM
9 LNA_N
RFIN
RFIN
3.3p 100p
22n TOKO LL2012
F22NJ
14107
3.3p 100p
39n TOKO LL2012
F39NJ
Figure 6. Input matching network without SAW filter
14108
Please notify that for all coupling conditions (see
figures 5 and 6), the bond wire inductivity of the LNA
ground is compensated. C3 forms a series resonance
circuit together with the bond wire. L = 25 nH is a feed
inductor to establish a DC path. Its value is not critical but
must be large enough not to detune the series resonance
circuit. For cost reduction this inductor can be easily
printed on the PCB. This configuration improves the
sensitivity of the receiver by about 1 dB to 2 dB.
Analog Signal Processing
IF Amplifier
The signals coming from the RF front end are filtered by
the fully integrated 4th-order IF filter. The IF center
frequency is fIF = 1 MHz for applications where
fRF = 315 MHz or fRF = 433.92 MHz is used. For other
RF input frequencies refer to table 1 to determine the
center frequency.
The U3741BM is available with 2 different IF
bandwidths. U3741BM-M2, the version with
BIF = 300 kHz, is well suited for ASK systems where the
TEMIC PLL transmitter U2741B is used. The receiver
U3741BM - M3 employs an IF bandwidth of
fIF = 600 kHz. This version can be used together with the
U2741B in FSK and ASK mode. If used in ASK
applications, it allows higher tolerances for the receiver
and PLL transmitter crystals. SAW transmitters exhibit
much higher transmit frequency tolerances compared to
PLL transmitters. Generally, it is necessary to use
BIF = 600 kHz together with such transmitters.
Rev. A1, 15-Oct-98
Preliminary Information
5 (25)
5 Page 
U3741BM
( Lim_min = 14, Lim_max = 24 )
Enable IC
Bitcheck failed ( CV_Lim < Lim_min )
Bitcheck
Dem_out
1/2 Bit
Bitcheck–Counter
0 1 2 3 4 5 6 1 2 3 4 5 6 7 8 9 10 11 12
Startup – Mode
Bitcheck – Mode
0
Sleep–Mode
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Figure 14. Timing diagram for failed bitcheck (condition: CV_Lim < Lim_min)
( Lim_min = 14, Lim_max = 24 )
Enable IC
Bitcheck failed ( CV_Lim = Lim_max )
Bitcheck
Dem_out
1/2 Bit
Bitcheck–Counter
0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
Startup – Mode
Bitcheck – Mode
0
Sleep–Mode
Figure 15. Timing diagram for failed bitcheck (condition: CV_Lim < Lim_max)
Duration of the Bitcheck
If no transmitter signal is present during the bitcheck, the
output of the ASK/ FSK demodulator delivers random
signals. The bitcheck is a statistical process and TBitcheck
varies for each check. Therefore, an average value for
TBitcheck is given in the electrical characteristics.
TBitcheck depends on the selected baudrate range and on
TClk. A higher baudrate range causes a lower value for
TBitcheck resulting in a lower current consumption for
polling mode.
In the presence of a valid transmitter signal, TBitcheck is
dependant on the frequency of that signal, fSig and the
count of the checked bits, NBitcheck. A higher value for
NBitcheck thereby results in a longer period for TBitcheck
requiring a higher value for the transmitter pre-burst
TPreburst.
Receiving Mode
If the bitcheck is successful for all bits specified by
NBitcheck, the receiver switches to receiving mode.
According to figure 11, the internal data signal is
switched to Pin DATA in that case. A connected µC can
be woken up by the negative edge at Pin DATA. The
receiver stays in that condition until it is switched back to
polling mode explicitly.
Digital Signal Processing
The data from the ASK/ FSK demodulator (Dem_out) is
digitally processed in different ways and as a result
converted into the output signal data. This processing
depends on the selected baudrate range (BR_Range).
Figure 16 illustrates how Dem_out is synchronized by the
extended clock cycle TXClk. This clock is also used for the
Bitcheck counter. Data can change its state only after
TXClk elapsed. The edge-to-edge time period tee of the
Data signal as a result is always an integral multiple of
TXClk.
The minimum time period between two edges of the data
signal is limited to tee ≥ TDATA_min. This implies an
efficient suppression of spikes at the DATA output. At the
same time it limits the maximum frequency of edges at
DATA. This eases the interrupt handling of a connected
µC. TDATA_min is to some extent affected by the preceding
edge-to-edge time interval tee as illustrated in figure 17.
If tee is in between the specified bitcheck limits, the
following level is frozen for the time period
TDATA_min = tmin1, in case of tee being outside that
bitcheck limits TDATA_min = tmin2 is the relevant stable
time period.
The maximum time period for DATA to be Low is limited
to TDATA_L_max. This function is employed to ensure a
finite response time in programming or switching off the
receiver via Pin DATA. TDATA_L_max is thereby longer
than the maximum time period indicated by the
transmitter data stream. Figure 18 gives an example
where Dem_out remains Low after the receiver is in
receiving mode.
Rev. A1, 15-Oct-98
Preliminary Information
11 (25)
11 Page | ||
| Páginas | Total 25 Páginas | |
| PDF Descargar | [ Datasheet U3741BM.PDF ] | |
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