|
|
82545EMのメーカーはIntelです、この部品の機能は「Gigabit Ethernet Controller」です。 |
部品番号 | 82545EM |
| |
部品説明 | Gigabit Ethernet Controller | ||
メーカ | Intel | ||
ロゴ | |||
このページの下部にプレビューと82545EMダウンロード(pdfファイル)リンクがあります。 Total 28 pages
www.DataSheet4U.com
82545EM Gigabit Ethernet Controller
Specification Update
June 6, 2006
The 82545EM Gigabit Ethernet Controller may contain design defects or errors known as errata that may cause the product to deviate
from published specifications. Current characterized errata are documented in this Specification Update.
i
1 Page 82545EM GIGABIT ETHERNET CONTROLLER SPECIFICATION UPDATE
CONTENTS
CONTENTS .........................................................................................................................................................1
PREFACE ............................................................................................................................................................4
NOMENCLATURE ..............................................................................................................................................4
COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE ..............................................................4
GENERAL INFORMATION .................................................................................................................................5
82545EM Component Marking Information ..................................................................................................5
SUMMARY TABLE OF CHANGES ....................................................................................................................6
Codes Used in Summary Tables ..................................................................................................................6
www.DataSheet4U.cSoPmECIFICATION CHANGES ..............................................................................................................................9
ERRATA ............................................................................................................................................................10
1. Collision/ASF/Manageability Data Re-Transmit Problem ..................................................................10
2. DMA and ASF/Manageability Concurrency Problems.......................................................................10
3. MDI/MDI-X Crossover Auto-Detection Not Working..........................................................................11
4. ASF/Manageability Transmit and Receive Not Functional in D3 State without APM ........................11
5. Wake-Up Disable Control for TCO / Manageability Packets .............................................................11
6. ASF State Machines Out of Sync on Power Up ................................................................................11
7. Short Packets under Heavy Transmit Load.......................................................................................12
8. 1.5V Regulator Control Circuit Start Up.............................................................................................12
9. PCI-X Bus Collisions with Some Chipsets.........................................................................................13
10. Retransmit Requests for 10Mb Half-Duplex Collisions......................................................................13
11. Excessive PCI Bus Hold Time ...........................................................................................................13
12. Bus Initialization with Some Chipsets ................................................................................................14
13. SMBALRT# Output Driven in ASF Mode...........................................................................................14
14. ASF Lockup upon Resetting MAC .....................................................................................................14
15. REQ# Pin Requires Pull-Up Resistor in PCI-X Mode........................................................................15
16. MWI Transactions May Terminate on Non-Cacheline Boundary ......................................................15
17. Some LEDs Asserted in D3 state with Wakeup and Manageability Disabled ...................................15
18. PCI-X Maximum Read Burst Size When Programmed Beyond Capability .......................................16
19. Master-Aborts with Some Chipsets during Driver-Initiated Controller Reset.....................................16
20. LSO Premature Descriptor Write Back.............................................................................................16
21. XOFF from Link Partner can Pause Flow-Control (XON/XOFF) Transmission................................17
22. Transmit Descriptor use of RS for non-data (Context & Null) Descriptors .......................................17
23. Address Error Crossing 64KB Boundary during PCI-X Packet Receives or Descriptor Writes........17
24. Intermittent Issues with TCO Receive Packets in IPMI Mode ...........................................................18
25. Message Signaled Interrupt Feature May Corrupt Write Transactions .............................................18
26. Link Establishment or Communication Problems in
Fiber Mode When Link Partner Does Not Fully Comply with the IEEE 802.3 Specification..............19
27. Wakeup Packet Memory (WUPM) cleared upon reset......................................................................19
28. Unexpected RCMP ACK packets in ASF mode ................................................................................19
29. Exceeding PCI Power Management
Specification Limit of 375mA current during reset and power state transitions .................................19
1
3Pages 82545EM GIGABIT ETHENET CONTROLLER SPECIFICATION UPDATE
PREFACE
This document is an update to published specifications. Specification documents for these products include:
• 82545EM Gigabit Ethernet Controller Datasheet, Intel Corporation.
• 82545EM Gigabit Ethernet Controller Design Guide, Intel Corporation.
• 82546EB Gigabit Ethernet Controller Networking Silicon Developer’s Manual + Appendices for
82545EM, 82540EM, 82544EI/GC, Intel Corporation.
This document is intended for hardware system manufactures and software developers of applications,
operating systems or tools. It may contain Specification Changes, Errata, and Specification Clarifications.
All 82545EM product documents are subject to frequent revision, and new order numbers will apply. New
documents may be added. Be sure you have the latest information before finalizing your design.
www.DataSheet4U.com
NOMENCLATURE
Specification Changes are modifications to the current published specifications. These changes will be
incorporated in the next release of the specifications.
Errata are design defects or errors. Errata may cause device behavior to deviate from published
specifications. Hardware and software designed to be used with any given stepping must assume that all
errata documented for that stepping are present on all devices.
Specification Clarifications describe a specification in greater detail or further highlight a specification’s
impact to a complex design situation. These clarifications will be incorporated in the next release of the
specifications.
Documentation Changes include typos, errors, or omissions from the current published specifications. These
changes will be incorporated in the next release of the specifications.
COMPONENT IDENTIFICATION VIA PROGRAMMING INTERFACE
82545EM controller steppings will be identified by the following register contents:
Stepping
82545EM A0
82545EM A1
Vendor ID
8086h
8086h
Device ID
100Fh
100Fh
Revision Number
00h
01h
These devices also provide identification data through the Test Access Port.
4
6 Page | |||
ページ | 合計 : 28 ページ | ||
|
PDF ダウンロード | [ 82545EM データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
82545EM | Gigabit Ethernet Controller | Intel |