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PDF MT8985 Data sheet ( Hoja de datos )
| Número de pieza | MT8985 | |
| Descripción | Enhanced Digital Switch | |
| Fabricantes | Zarlink Semiconductor | |
| Logotipo |  |
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CMOS ST-BUSTM Family MT8985
Enhanced Digital Switch
Data Sheet
Features
• 256 x 256 channel non-blocking switch
• Programmable frame integrity for wideband
channels
• Automatic identification of ST-BUS/GCI interface
backplanes
• Per channel tristate control
• Patented message mode
www.DataShee•t4UN.comn-multiplexed microprocessor interface
• Single +5 volt supply
• Available in DIP-40, PLCC-44 and QFP-44
packages
• Pin compatible with MT8980 device
Applications
• Medium size digital switch matrices
• Hyperchannel switching (e.g., ISDN H0)
• ST-BUS/MVIP™ interface functions
• Serial bus control and monitoring
• Centralized voice processing systems
• Data multiplexer
Description
The MT8985 Enhanced Digital Switch device is an
upgraded version of the popular MT8980D Digital
September 2005
Ordering Information
MT8985AE 40 Pin PDIP
MT8985AP 44 Pin PLCC
MT8985AL 44 Pin MQFP
MT8985APR 44 Pin PLCC
MT8985AP1 44 Pin PLCC*
MT8985APR1 44 Pin PLCC*
MT8985AE1 40 Pin PDIP*
MT8985AL1 44 Pin MQFP*
Tubes
Tubes
Trays
Tape & Reel
Tubes
Tape & Reel
Tubes
Trays
*Pb Free Matte Tin
-40°C to +85°C
Switch (DX). It is pin compatible with the MT8980D and
retains all of the MT8980D's functionality. This VLSI
device is designed for switching PCM-encoded voice
or data, under microprocessor control, in digital
exchanges, PBXs and any ST-BUS/MVIP
environment. It provides simultaneous connections for
up to 256 64 kb/s channels. Each of the eight serial
inputs and outputs consist of 32 64 kbit/s channels
multiplexed to form a 2048 kbit/s stream. As the main
function in switching applications, the device provides
per-channel selection between variable or constant
throughput delays. The constant throughput delay
feature allows grouped channels such as ISDN H0 to
be switched through the device maintaining its
sequence integrity. The MT8985 is ideal for medium
sized mixed voice/data switch and voice processing
applications.
C4i F0i
VDD VSS
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
Serial
to
Parallel
Converter
Data
Memory
Frame
Counter
Control Register
Control Interface
Output
MUX
Connection
Memory
Parallel
to
Serial
Converter
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
DS CS R/W A5/ DTA D7/
A0 D0
CSTo
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1997-2005, Zarlink Semiconductor Inc. All Rights Reserved.
1 page  
MT8985
Data Sheet
In message mode the CPU writes data to the Connect Memory Low locations which correspond to the output link
and channel number. The contents of the Connect Memory Low are transferred to the parallel to serial converter
one channel before it is to be output. The Connect Memory Low data is transmitted each frame to the output until it
is changed by the CPU.
The per-channel functions available in the MT8985 are controlled by the Connect Memory High bits, which
determine whether individual output channels are selected into specific conditions such as: message or connection
mode, variable or constant throughput delay modes, output drivers enabled or in three-state condition. In addition,
the Connect Memory High provides one bit to allow the user to control the state of the CSTo output pin.
If an output channel is set to three-state condition, the TDM serial stream output will be placed in high impedance
during that channel time. In addition to the per-channel three-state control, all channels on the TDM outputs can be
placed in high impedance at one time by pulling the ODE input pin in LOW. This overrides the individual per-
channel programming on the Connect Memory High bits.
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The Connect Memory data is received via the Microprocessor Interface at D0-D7 lines. The addressing of the
MT8985 internal registers, Data and Connect memories is performed through address input pins and some bits of
the device's Control register. The higher order address bits come from the Control register, which may be written or
read through the microprocessor interface. The lower order address bits come directly from the external address
line inputs. For details on the device addressing, see Software Control and Control register description.
Serial Interface Timing
The MT8985 master clock (C4i) is a 4.096 MHz allowing serial data link configuration at 2.048 Mb/s to be
implemented. The MT8985 frame synchronization pulse can be formatted according to ST-BUS or GCI interface
specifications; i.e., the frame pulse can be active in HIGH (GCI) or LOW (ST-BUS). The MT8985 device
automatically detects the presence of an input frame pulse and identifies the type of backplane present on the serial
interface. Upon determining the correct interface connected to the serial port, the internal timing unit establishes the
appropriate serial data bit transmit and sampling edges. In ST-BUS mode, every second falling edge of the 4.096
MHz clock marks a bit boundary and the input data is clocked in by the rising edge, three quarters of the way into
the bit cell. In GCI mode, every second rising edge of the 4.096 MHz clock marks the bit boundary while data
sampling is performed during the falling edge, at three quarters of the bit boundaries.
Delay through the MT8985
The transfer of information from the input serial streams to the output serial streams results in a delay through the
MT8985 device. The delay through the MT8985 device varies according to the mode selected in the V/C bit of the
connect memory high.
Variable Delay Mode
The delay in this mode is dependent only on the combination of source and destination channels and it is not
dependent on the input and output streams. The minimum delay achievable in the MT8985 device is 3 time slots. In
the MT8985 device, the information that is to be output in the same channel position as the information is input
(position n), relative to frame pulse, will be output in the following frame (channel n, frame n+1). The same occurs if
the input channel has to be output in the two channels succeeding (n+1 and n+2) the channel position as the
information is input.
The information switched to the third timeslot after the input has entered the device (for instance, input channel 0 to
output channel 3 or input channel 30 to output channel 1), is always output three channels later.
Any switching configuration that provides three or more timeslots between input and output channels, will have a
throughput delay equal to the difference between the output and input channels; i.e., the throughput delay will be
less than one frame. Table 1 shows the possible delays for the MT8985 device in Variable Delay mode:
5
Zarlink Semiconductor Inc.
5 Page 
MT8985
Data Sheet
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••••••
Server 2
ISDN Desktops
(2B+D)
••••••
Server 1
T1/E1
T1
Server 3
T1
E1
Server 4
Isochronous Network
n x 64
Connections
(e.g. Video)
Figure 8a - Private Isochronous Network
Low Latency Isochronous Network
In today's local working group environment, there is an increasing demand for solutions on interconnection of
desktop and telephone systems so that mixed voice, data and video services can be grouped together in a reliable
network allowing the deployment of multimedia services. Existing multimedia applications require a network with
predictable data transfer delays that can be implemented at a reasonable cost. The Low Latency Isochronous
Network is one of the alternatives that system designers have chosen to accommodate this requirement (see
Figure 8a). This network can be implemented using existing TDM transmission media devices such as ISDN Basic
(S or U) and Primary rates trunks (T1 and CEPT) to transport mixed voice and data signals in grouped time slots;
for example, 2B channels in case of ISDN S or U interfaces or up to 32 channels in case of a CEPT link.
Figure 8b shows a more detailed configuration whereby several PCs are connected to form an Isochronous
network. Several services can be interconnected within a single PC chassis through the standardized Multi Vendor
Integration Protocol (MVIP). Such an interface allows the distribution and interconnection of services like voice
mail, integrated voice response, voice recognition, LAN gateways, key systems, fax servers, video cards, etc.
The information being exchanged between cards through the MVIP interface on every computer as well as between
computers through T1 or CEPT links is, in general, of mixed type where 64Kb/s and N*64Kb/s channels are
grouped together. When such a mixed type of data is transferred between cards within one chassis or from one
computer to another, the sequence integrity of the concatenated channels has to be maintained. The MT8985
device suits this application and can be used to form a complete non-blocking switch matrix of 512 channels (see
Figure 9). This allows 8 pairs of ST-BUS streams to be dedicated to the MVIP side whereas the remaining 8 pairs
are used for local ancillary functions in typical dual T1/E1 interface applications (Figure 10).
Another application of the MT8985 in an MVIP environment is to build an ISDN S-interface card (Figure 11). In this
card, 7 pairs of ST-BUS streams are connected to the MVIP interface while the remaining pair is reserved for the
interconnection of Zarlink MT8930 (SNIC), MT8992 (H-PHONE) and the MVIP interface.
11
Zarlink Semiconductor Inc.
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet MT8985.PDF ] | |
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