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PDF ST92186B Data sheet ( Hoja de datos )
| Número de pieza | ST92186B | |
| Descripción | 8/16-BIT MCU | |
| Fabricantes | ST Microelectronics | |
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ST92186B
8/16-BIT MCU FOR TV APPLICATIONS
WITH UP TO 32K ROM AND ENHANCED ON-SCREEN-DISPLAY
s Register file based 8/16 bit Core Architecture
with RUN, WFI, and HALT modes
www.DataSheet4Us.co-m10 to 70°C Operating Temperature Range
s 24 MHz Operation @5V+-10%
s Minimum instruction cycle time: 250ns at 16
MHz internal clock, 165ns at 24 MHz internal
clock
s 24 or 32 Kbytes ROM
s 640 bytes of on-chip static RAM
s 256 bytes of Register file
s 256 bytes of display RAM (OSDRAM)
s 32-pin Shrink DIP and 42-pin Shrink DIP
packages
s 26 (SDIP42) or 17 (SDIP32) fully programmable
I/O pins
s Flexible Clock controller for OSD and Core
clocks, running from one single low frequency
external crystal
s Enhanced Display Controller with rows of up to
63 characters per row
– 50/60Hz and 100/120 Hz operation
– 525/625 lines operation, 4/3 or 16/9 format
– Interlaced and progressive scanning
– 18x26 or 9x13 character matrix
– 256 (18x26) characters, 1024 (9x13) charac-
ters definable in ROM by user
– 512 possible colors, in 4x16-entry palettes
– 2 x 16-entry palettes for Foreground, and 2 x
16-entry palettes for Background
– 8 levels of translucency on Fast Blanking
– Serial, Parallel, and Extended Parallel At-
tributes modes
– 7 character sizes in 18x26 mode, 4 in 9x13
– Rounding, Fringe, Scrolling, Flashing, Shad-
owing, Italics, Semi-transparent
s 5-channel (SDIP42) or 3-channel (SDIP32)
Analog-to-Digital converter with 6-bit accuracy
s 16-bit Watchdog timer with 8-bit prescaler
s 14-bit Voltage Synthesis for tuning reference
voltage with 2 outputs (SDIP42) for 2 tuners or 1
output (SDIP32) for 1 tuner
PSDIP32
PSDIP42
s 16-bit standard timer with 8-bit prescaler
s 6 (SDIP42) or 4 (SDIP32) 8-bit programmable
PWM outputs
s NMI and 8 (SDIP42) or 6 (SDIP32) external
interrupts
s Infra-Red signal digital pre-processor
s Rich instruction set and 14 addressing modes
s Versatile Development Tools, including C-
Compiler, Assembler, Linker
s Source Level Debugger, Emulator and Real-
Time Operating Systems available from third-
parties
s Windows Based OSD Font and Screen Editor
s EPROM and OTP devices available
(ST92E196A9 and ST92T196A9)
DEVICE SUMMARY
Device
Program Memory Package
ST92186B3
ST92186B4
24K SDIP32/SDIP42
32K SDIP32/SDIP42
September 2003
.
1/148
2
1 page  
1 GENERAL DESCRIPTION
ST92186B - GENERAL DESCRIPTION
1.1 INTRODUCTION
The ST92186B family brings the enhanced ST9
register-based architecture to a new range of high-
performance microcontrollers specifically de-
signed for TV applications. Their performance de-
rives from the use of a flexible 256-register pro-
gramming model for ultra-fast context switching
and real-time event response. The intelligent on-
www.DataSheet4Uc.choimp peripherals offload the ST9 core from I/O and
data management processing tasks allowing criti-
cal application tasks to get the maximum use of
core resources. The ST9 MCU devices support
low power consumption and low voltage operation
for power-efficient and low-cost embedded sys-
tems.
1.1.1 Core Architecture
The nucleus of the ST92186B is the enhanced
ST9 Core that includes the Central Processing
Unit (CPU), the register file and the interrupt con-
troller.
Three independent buses are controlled by the
Core: a 16-bit memory bus, an 8-bit register ad-
dressing bus and a 6-bit interrupt bus which con-
nects the interrupt controller in the on-chip periph-
erals with the core.
This multiple bus architecture makes the ST9 fam-
ily devices highly efficient for accessing on and
off-chip memory and fast exchange of data with
the on-chip peripherals.
The general-purpose registers can be used as ac-
cumulators, index registers, or address pointers.
Adjacent register pairs make up 16-bit registers for
addressing or 16-bit processing. Although the ST9
has an 8-bit ALU, the chip handles 16-bit opera-
tions, including arithmetic, loads/stores, and mem-
ory/register and memory/memory exchanges.
Many opcodes specify byte or word operations,
the hardware automatically handles 16-bit opera-
tions and accesses.
For interrupts or subroutine calls, the CPU uses a
system stack in conjunction with the stack pointer
(SP). A separate user stack has its own SP. The
separate stacks, without size limitations, can be in
on-chip RAM (or in Register File) or off-chip mem-
ory.
1.1.2 Instruction Set
The ST9 instruction set consists of 94 instruction
types, including instructions for bit handling, byte
(8-bit) and word (16-bit) data, as well as BCD and
Boolean formats. Instructions have been added to
facilitate large program and data handling through
the MMU, as well as to improve the performance
and code density of C Function calls. 14 address-
ing modes are available, including powerful indi-
rect addressing capabilities.
The ST9’s bit-manipulation instructions are set,
clear, complement, test and set, load, and various
logic instructions (AND, OR, and XOR). Math func-
tions include add, subtract, increment, decrement,
decimal adjust, multiply, and divide.
1.1.3 Operating Modes
To optimize performance versus the power con-
sumption of the device, ST9 devices now support
a range of operating modes that can be dynami-
cally selected depending on the performance and
functionality requirements of the application at a
given moment.
Run Mode. This is the full speed execution mode
with CPU and peripherals running at the maximum
clock speed delivered by the Phase Locked Loop
(PLL) of the Clock Control Unit (CCU).
Slow Mode. Power consumption can be signifi-
cantly reduced by running the CPU and the periph-
erals at reduced clock speed using the CPU Pres-
caler and CCU Clock Divider.
Wait For Interrupt Mode. The Wait For Interrupt
(WFI) instruction suspends program execution un-
til an interrupt request is acknowledged. During
WFI, the CPU clock is halted while the peripheral
and interrupt controller keep running at a frequen-
cy programmable via the CCU. In this mode, the
power consumption of the device can be reduced
by more than 95% (LP WFI).
Halt Mode. When executing the HALT instruction,
and if the Watchdog is not enabled, the CPU and
its peripherals stop operating and the status of the
machine remains frozen (the clock is also
stopped). A reset is necessary to exit from Halt
mode.
5/148
5 Page 
ST92186B - GENERAL DESCRIPTION
PIN DESCRIPTION (Cont’d)
1.2.1 I/O Port Configuration
All ports can be individually configured as input, bi-
directional, output, or alternate function. Refer to
the Port Bit Configuration Table in the I/O Port
Chapter.
No I/O pins have any physical weak pull-up capa-
bility (they will show no pull-up if they are pro-
grammed in the "weak pull-up" software mode).
www.DataSheet4UIc.nchopomuotsilnegveblsetwcaenenbTeTLseoler cCteMdOoSninapubt iltevbealssisforbIy/
O port pin except for P2.(5:4,0), P3.(6:4,1:0),
P4.(1:0) which are implemented with a Schmitt
trigger function.
All port output configurations can be software se-
lected on a bit basis to provide push-pull or open
drain driving capabilities. For all ports, when con-
figured as open-drain, the voltage on the pin must
never exceed the VDD power line value (refer to
Electrical characteristics section).
Warning:
Some I/Os are not bonded in the SDIP32 pack-
age. You must configure these unbonded I/Os (i.e.
P2.1, P2.2, P3.1, P3.5, P3.7, P5.1, P5.2, P5.5 and
P5.6) as output push-pull at the very first begin-
ning of your software and never change this con-
figuration after initialization. This will avoid unpre-
dictable software behavior.
1.2.2 I/O Port Reset State
I/Os are reset asynchronously as soon as the RE-
SET pin is asserted low.
All I/Os are forced by the Reset in "weak pull-up"
configuration mode (but some are in high imped-
ance due to the lack of physical pull-up) except
P5.0 (refer to the Reset section) which is forced
into the "Push-Pull Alternate Function" mode until
being reconfigured by software.
Warning:
When a common pin is declared to be connected
to an alternate function input and to an alternate
function output, the user must be aware of the fact
that the alternate function output signal always in-
puts to the alternate function module declared as
input.
When any given pin is declared to be connected to
a digital alternate function input, the user must be
aware of the fact that the alternate function input is
always connected to the pin. When a given pin is
declared to be connected to an analog alternate
function input (ADC input for example) and if this
pin is programmed in the "AF-OD" mode, the digit-
al input path is disconnected from the pin to pre-
vent any DC consumption.
Table 3. I/O Port Characteristics
Port 0[4:3]
Port 2.0
Port 2[3:1]
Port 2[5:4]
Port 2[7:6]
Port 3[0:1]
Port 3.2
Port 3[6:4]
Port 3.7
Port 4[1:0]
Port 4[7:6]
Port 5.0
Port 5[2:1]
Port 5[6:5]
Input
TTL/CMOS
Schmitt trigger
TTL/CMOS
Schmitt trigger
TTL/CMOS
Schmitt trigger
TTL/CMOS
Schmitt trigger
TTL/CMOS
Schmitt trigger
TTL/CMOS
TTL/CMOS
TTL/CMOS
TTL/CMOS
Output
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Push-Pull/OD
Weak Pull-Up
No
No
No
No
No
No
No
No
No
No
No
No
No
No
Reset State
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Bidirectional
Push-Pull AF Out
Bidirectional
Bidirectional
Legend: OD = Open Drain, AF = Alternate Function
11/148
11 Page | ||
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| PDF Descargar | [ Datasheet ST92186B.PDF ] | |
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