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PDF STEL-1175 Data sheet ( Hoja de datos )
| Número de pieza | STEL-1175 | |
| Descripción | 32-Bit Resolution CMOS Phase Modulated Numerically Controlled Oscillator | |
| Fabricantes | Intel | |
| Logotipo |  |
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STEL-1175
Data Sheet
STEL-1175+125
(125 MHz)
32-Bit Resolution CMOS
Phase Modulated
Numerically
Controlled Oscillator
R
1 page  
clock edges, and thereafter will remain at the value
corresponding to zero phase (801H) until new frequency
or phase modulation data is loaded with the FRLD or
PHLD inputs after the RESET returns high.
CLOCK
All synchronous functions performed within the NCO are
referenced to the rising edge of the CLOCK input. The
CLOCK signal should be nominally a square wave at a
maximum frequency of 125 MHz. A non-repetitive
CLOCK waveform is permissible as long as the minimum
duration positive or negative pulse on the waveform is
always greater than 4 nanoseconds.
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The Chip Select input is used to control the writing of
data into the chip. It is active low. When this input is high
all data writing via the DATA7-0 bus is inhibited.
DATA7 through DATA0
The 8-bit DATA7-0 bus is used to program the two 32-bit
∆-Phase Registers and the 12-bit Phase Modulation
Register. DATA0 is the least significant bit of the bus. The
data programmed into the ∆-Phase registers in this way
determines the output frequency of the NCO.
ADDR3 through ADDR0
The four address lines ADDR3-0 control the use of the
DATA7-0 bus for writing frequency data to the ∆-Phase
Buffer Registers, and phase data to the Phase Buffer
Register, as shown in the tables:
ADDR3 ADDR1 ADDR0 Register Field
0 0 0 ∆-Phase Bits 7 0(LSB)
0 0 1 ∆-Phase Bits15 8
0 1 0 ∆-Phase Bits 23 16
0 1 1 ∆-Phase Bits 31 24
1 0 0 Phase Bits 3* 0(LSB)
1 0 1 Phase Bits 11* 4
ADDR3 ADDR2
00
01
1X
Register Selected
∆-Phase Buffer Register 'A'
∆-Phase Buffer Register 'B'
Phase Buffer Register
* Note: The Phase Buffer Register is a 12-bit register.
When the least significant byte of this register is selected
(ADDR3-0 =1X00), DATA7-4 is written into Bits 30 of
the register. In all cases, it is not necessary to reload
unchanged bytes, and the byte loading sequence may be
random.
WRSTB
The Write Strobe input is used to latch the data on the
DATA7-0 bus into the device. On the rising edge of the
WRSTB input, the information on the 8-bit data
bus is transferred to the buffer register selected by the
ADDR3-0bus.
FRSEL
The Frequency Register Select line controls the mux
which selects the ∆-Phase Buffer Register in use. When
this signal is high ∆-Phase Buffer Register 'A' is selected as
the source for the ∆-Phase Register, and the frequency
corresponding to the data stored in this register will be
generated by the NCO after the next FRLD command.
When this line is low, ∆-Phase Buffer Register 'B' is
selected as the source.
FRLD
The Frequency Load input is used to control the transfer
of the data from the ∆-Phase Buffer Registers to the ∆-
Phase Register. The data at the output of the Mux Block
must be valid during the clock cycle following the falling
edge of FRLD. The data is then transferred during the
subsequent cycle. The frequency of the NCO output will
change 19 rising clock edges after the FRLD command
due to pipelining delays.
PHSEL
The Phase Source Select input selects the source of data
for the Phase ALU. When it is high the source is the Phase
Buffer Register. It is loaded from the
DATA7-
0 bus by setting address line ADDR3 high, as shown in the
tables. When PHSEL is low, the sources for the phase
modulation data are the DATA7-0 and ADDR3-0 inputs,
and the data will be loaded independently of the states of
WRSTB and CSEL. The data on these 12 inputs is
presented directly as a parallel 12-bit word to the Phase
ALU, allowing high-speed phase modulation. The 12-bit
value is latched into the Phase ALU by means of the PHLD
input. The data on the ADDR3-0lines is mapped onto Phase
Bits 3 to 0 and the data on the DATA7-0 lines are mapped
onto Phase Bits 11 to 4 in this case. When using the parallel
phase load mode CSEL and/or WRSTB should remain
high to ensure that the phase data is not written into the
phase and frequency buffer registers of the STEL-1175.
PHLD
The Phase Load input is used to control the latching of
the Phase Modulation data into the Phase ALU. The 12-
bit data at the output of the Phase Modulation Control
Block must be valid during the clock cycle following the
falling edge of PHLD. The data is then transferred during
the subsequent cycle. The 12-bit phase data is added to the
12 most significant bits of the accumulator output, so that
the MSB of the phase data represents a 180° phase change.
The source of this data will be determined by the state of
5 STEL-1175+125
5 Page 
HIGH-SPEED FREQUENCY CHANGE
CLOCK
1 2 3 45 6 7 8 9
WRSTB
ADDR
0111
0000
0001 0010
0011 0100
0101
0110
0111
0000
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FRLD
FRSEL
APPLICATIONS INFORMATION
USING THE STEL-1175
IN A HIGH-SPEED
PHASE MODULATOR
By routing the data and address
lines from the microcontroller via
2:1 multiplexers (e.g. 74HC157)
the MNCO can be set up from the
microcontroller and then phase
modulated at high-speed from an
external source. The PHSEL line
should be set to a logic 0 to enable
this mode of operation. The
system shown modulates all 12
bits. In a typical PSK system only
1 to 4 bits of modulation will be
used, simplifying the system
considerably.
FROM
µC
WRITE
FREQ. LOAD
DATA0-7
ADDR0-3
PHASE0-11
FROM
PHASE
MOD.
FREQ. /PH SEL
PHASE LOAD
4A
4B
A/B
4A
4B
A/B
4A
4B
A/B
WRSTB
FRLD
D0
D3
D4
STEL-1175
MNCO
D7
A0
A3
PHLD
WBP 54815.c-11/20/98
SPECTRAL PURITY
In many applications the NCO is used with a digital to
analog converter (DAC) to generate an analog waveform
which approximates an ideal sinewave. The spectral purity
of this synthesized waveform is a function of many
variables including the phase and amplitude quantization,
the ratio of the clock frequency to output frequency, and
the dynamic characteristics of the DAC.
The sine or cosine signals generated by the STEL-1175
have 12 bits of amplitude resolution and 13 bits of phase
resolution which results in spurious levels which are
theoretically at least 75 dB down. The highest output
frequency the NCO can generate is half the clock
frequency (fc/2), and the spurious components at
frequencies greater than fc/2 can be removed by filtering.
11 STEL-1175+125
11 Page | ||
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| PDF Descargar | [ Datasheet STEL-1175.PDF ] | |
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