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PDF MX26LV008B Data sheet ( Hoja de datos )
| Número de pieza | MX26LV008B | |
| Descripción | 8M-BIT [1M x 8] CMOS SINGLE VOLTAGE 3V ONLY HIGH SPEED eLiteFlashTM MEMORY | |
| Fabricantes | Macronix International | |
| Logotipo |  |
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MX26LV008T/B
Macronix NBitTM Memory Family
8M-BIT [1M x 8] CMOS SINGLE VOLTAGE
3V ONLY HIGH SPEED eLiteFlashTM MEMORY
FEATURES
• Extended single - supply voltage range 3.0V to 3.6V
• 1,048,576 x 8
• Single power supply operation
- 3.0V only operation for read, erase and program
www.DataSheet4Uo.cpoemration
• Fast access time: 55/70ns
• Low power consumption
- 30mA maximum active current
- 30uA typical standby current
• Command register architecture
- Byte Programming (55us typical)
- Sector Erase (Sector structure 16K-Bytex1,
8K-Bytex2, 32K-Bytex1, and 64K-Byte x15)
• Auto Erase (chip & sector) and Auto Program
- Automatically erase any combination of sectors with
Erase Suspend capability.
- Automatically program and verify data at specified
address
• Status Reply
- Data# polling & Toggle bit for detection of program
and erase operation completion.
• Ready/Busy# pin (RY/BY#)
- Provides a hardware method of detecting program or
erase operation completion.
• 2,000 minimum erase/program cycles
• Latch-up protected to 100mA from -1V to VCC+1V
• Package type:
- 40-pin TSOP
• Compatibility with JEDEC standard
- Pinout and software compatible with single-power
supply Flash
• 20 years data retention
GENERAL DESCRIPTION
The MX26LV008T/B is a 8-mega bit Flash memory or-
ganized as 1M bytes of 8 bits. MXIC's Flash memories
offer the most cost-effective and reliable read/write non-
volatile random access memory. The MX26LV008T/B
is packaged in 40-pin TSOP. It is designed to be repro-
grammed and erased in system or in standard EPROM
programmers.
The standard MX26LV008T/B offers access time as fast
as 55ns, allowing operation of high-speed microproces-
sors without wait states. To eliminate bus contention,
the MX26LV008T/B has separate chip enable (CE#) and
output enable (OE#) controls.
MXIC's Flash memories augment EPROM functionality
with in-circuit electrical erasure and programming. The
MX26LV008T/B uses a command register to manage
this functionality. The command register allows for 100%
TTL level control inputs and fixed power supply levels
during erase and programming, while maintaining maxi-
mum EPROM compatibility.
MXIC Flash technology reliably stores memory contents
even after 2,000 erase and program cycles. The MXIC
cell is designed to optimize the erase and programming
mechanisms. In addition, the combination of advanced
tunnel oxide processing and low internal electric fields
for erase and program operations produces reliable cy-
cling. The MX26LV008T/B uses a 3.0V~3.6V VCC sup-
ply to perform the High Reliability Erase and auto Pro-
gram/Erase algorithms.
The highest degree of latch-up protection is achieved
with MXIC's proprietary non-epi process. Latch-up pro-
tection is proved for stresses up to 100 milliamps on
address and data pin from -1V to VCC + 1V.
P/N:PM1057
REV. 1.0, NOV. 08, 2004
1
1 page  
BLOCK DIAGRAM
MX26LV008T/B
www.DataSheet4U.com
CE#
OE#
WE#
RESET#
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
A0-A19
ADDRESS
LATCH
AND
BUFFER
MX26LV008T/B
FLASH
ARRAY
ARRAY
SOURCE
HV
Y-PASS GATE
STATE
REGISTER
COMMAND
DATA
DECODER
SENSE
AMPLIFIER
PGM
DATA
HV
PROGRAM
DATA LATCH
COMMAND
DATA LATCH
Q0-Q7
I/O BUFFER
P/N:PM1057
REV. 1.0, NOV. 08, 2004
5
5 Page 
MX26LV008T/B
time of tREADY (during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is completed within a
time of tREADY (not during Embedded Algorithms).The
system can read data tRH after the RESET# pin returns
to VIH.
Refer to the AC Characteristics tables for RESET#
www.DataSheetp4aUr.caommeters and to Figure 14 for the timing diagram.
READ/RESET COMMAND
The read or reset operation is initiated by writing the
read/reset command sequence into the command reg-
ister. Microprocessor read cycles retrieve array data.
The device remains enabled for reads until the command
register contents are altered.
If program-fail or erase-fail happen, the write of F0H will
reset the device to abort the operation. A valid com-
mand must then be written to place the device in the
desired state.
SILICON-ID READ COMMAND
Flash memories are intended for use in applications where
the local CPU alters memory contents. As such, manu-
facturer and device codes must be accessible while the
device resides in the target system. PROM program-
mers typically access signature codes by raising A9 to
a high voltage (VID). However, multiplexing high volt-
age onto address lines is not generally desired system
design practice.
The MX26LV008T/B contains a Silicon-ID-Read opera-
tion to supple traditional PROM programming methodol-
ogy. The operation is initiated by writing the read silicon
ID command sequence into the command register. Fol-
lowing the command write, a read cycle with A1=VIL,
A0=VIL retrieves the manufacturer code of C2H. A read
cycle with A1=VIL, A0=VIH returns the device code of
3EH for MX26LV008T, 37H for MX26LV008B.
"unlock" write cycles. These are followed by writing the
"set-up" command 80H. Two more "unlock" write cycles
are then followed by the chip erase command 10H or
sector erase command 30H.
The Automatic Chip Erase does not require the device
to be entirely pre-programmed prior to executing the Au-
tomatic Chip Erase. Upon executing the Automatic Chip
Erase, the device will automatically program and verify
the entire memory for an all-zero data pattern. When the
device is automatically verified to contain an all-zero
pattern, a self-timed chip erase and verify begin. The
erase and verify operations are completed when the data
on Q7 is "1" at which time the device returns to the
Read mode. The system is not required to provide any
control or timing during these operations.
When using the Automatic Chip Erase algorithm, note
that the erase automatically terminates when adequate
erase margin has been achieved for the memory array
(no erase verification command is required).
If the Erase operation was unsuccessful, the data on
Q5 is "1"(see Table 7), indicating the erase operation
exceed internal timing limit.
The automatic erase begins on the rising edge of the
last WE# or CE# pulse, whichever happens first in the
command sequence and terminates when the data on
Q7 is "1" and the data on Q6 stops toggling for two con-
secutive read cycles, at which time the device returns
to the Read mode.
SET-UP AUTOMATIC CHIP/SECTOR ERASE
COMMANDS
Chip erase is a six-bus cycle operation. There are two
P/N:PM1057
11
REV. 1.0, NOV. 08, 2004
11 Page | ||
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