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7650SCB の電気的特性と機能

7650SCBのメーカーはIntersil Corporationです、この部品の機能は「ICL7650SCB」です。


製品の詳細 ( Datasheet PDF )

部品番号 7650SCB
部品説明 ICL7650SCB
メーカ Intersil Corporation
ロゴ Intersil Corporation ロゴ 




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7650SCB Datasheet, 7650SCB PDF,ピン配置, 機能
TM
Data Sheet
ICL7650S
April 2000
File Number 2920.5
2MHz, Super Chopper-Stabilized
Operational Amplifier
The ICL7650S Super Chopper-Stabilized Amplifier offers
exceptionally low input offset voltage and is extremely stable
with respect to time and temperature. It is a direct
replacement for the industry-standard ICL7650 offering
improved input offset voltage, lower input offset voltage
temperature coefficient, reduced input bias current, and
wider common mode voltage range. All improvements are
www.DataSheheigt4hUli.gchotmed in bold italics in the Electrical Characteristics
section. Critical parameters are guaranteed over the
entire commercial temperature range.
Intersil’s unique CMOS chopper-stabilized amplifier circuitry
is user-transparent, virtually eliminating the traditional
chopper amplifier problems of intermodulation effects,
chopping spikes, and overrange lockup.
The chopper amplifier achieves its low offset by comparing
the inverting and non-inverting input voltages in a nulling
amplifier, nulled by alternate clock phases. Two external
capacitors are required to store the correcting potentials on
the two amplifier nulling inputs; these are the only external
components necessary.
The clock oscillator and all the other control circuitry is
entirely self-contained. However the 14 lead version includes
a provision for the use of an external clock, if required for a
particular application. In addition, the ICL7650S is internally
compensated for unity-gain operation.
Features
Guaranteed Max Input Offset Voltage for All Temperature
Ranges
• Low Long-Term and Temperature Drifts of Input Offset
Voltage
Guaranteed Max Input Bias Current. . . . . . . . . . . . . .10pA
Extremely Wide Common Mode
Voltage Range . . . . . . . . . . . . . . . . . . . . . . . +3.5V to -5V
Reduced Supply Current . . . . . . . . . . . . . . . . . . . . . . 2mA
Guaranteed Minimum Output Source/Sink Current
• Extremely High Gain . . . . . . . . . . . . . . . . . . . . . . . .150dB
• Extremely High CMRR and PSRR . . . . . . . . . . . . . .140dB
• High Slew Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . .2.5V/µs
• Wide Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2MHz
• Unity-Gain Compensated
• Clamp Circuit to Avoid Overload Recovery Problems and
Allow Comparator Use
• Extremely Low Chopping Spikes at Input and Output
Improved, Direct Replacement for Industry-Standard
ICL7650 and other Second-Source Parts
Ordering Information
PART NUMBER
ICL7650SCPA-1
TEMP.
RANGE
(oC)
PACKAGE
0 to 70 8 Ld PDIP
ICL7650SCPD
ICL7650SCBA-1
ICL7650SCTV-1
0 to 70
0 to 70
0 to 70
14 Ld PDIP
8 Ld SOIC
8 Pin Metal Can
PKG.
NO.
E8.3
E14.3
M8.15
T8.C
Pinouts
ICL7650S (PDIP, SOIC)
TOP VIEW
CEXTA 1
-IN 2
+IN 3
V- 4
-
+
8 CEXTB
7 V+
6 OUTPUT
5 CRETN
ICL7650S (METAL CAN)
TOP VIEW
CEXTB
CEXTA 1
8
7 V+/CASE
-IN 2
-
+
6 OUTPUT
+IN 3
5 CRETN
4
V-
ICL7650S (PDIP)
TOP VIEW
CEXTB 1
CEXTA 2
NC (GUARD) 3
-IN 4
+IN 5
NC (GUARD) 6
V- 7
-
+
14 INT/EXT
13 EXT CLK IN
12 INT CLK OUT
11 V+
10 OUTPUT
9 OUT CLAMP
8 CRETN
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000

1 Page





7650SCB pdf, ピン配列
ICL7650S
Absolute Maximum Ratings
Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18V
Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . (V+ +0.3) to (V- -0.3)
Voltage on Oscillator Control Pins . . . . . . . . . . . . . . . . . . . . V+ to V-
Duration of Output Short Circuit. . . . . . . . . . . . . . . . . . . . . Indefinite
Current to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
While Operating (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA
Operating Conditions
Temperature Range
ICL7650SC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
Thermal Information
Thermal Resistance (Typical, Note 2)
θJA (oC/W) θJC (oC/W)
8 Lead PDIP Package . . . . . . . . . . . . . 120
N/A
14 Lead PDIP Package . . . . . . . . . . . .
80
N/A
8 Lead SOIC Package . . . . . . . . . . . . . 160
N/A
Metal Can Package . . . . . . . . . . . . . . . 160
75
Maximum Junction Temperature (Hermetic Package) . . . . . . . .175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -55oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
www.DataShee1t.4ULi.mcoitming input current to 100µA is recommended to avoid latchup problems. Typically 1mA is safe, however this is not guaranteed.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications VSUPPLY = ±5V. See Test Circuit, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
TEMP.
(oC)
Input Offset Voltage (Note 3)
VOS
25
0 to 70
Average Temperature Coefficient of
Input Offset Voltage (Note 3)
VOS/T
0 to 70
Change in Input Offset with Time
Input Bias Current |I(+)|, |I(-)|
VOS/T
IBIAS
25
25
0 to 70
Input Offset Current |I(-), |I(+)|
IOS
25
0 to 70
Input Resistance
Large Signal Voltage Gain (Note 3)
RIN
AVOL
RL = 10k, VO = ±4V
25
25
0 to 70
Output Voltage Swing (Note 4)
Common Mode Voltage Range (Note 3)
VOUT
CMVR
RL = 10k
RL = 100k
25
25
25
0 to 70
Common Mode Rejection Ratio
(Note 3)
CMRR CMVR = -5V to +3.5V
25
0 to 70
Power Supply Rejection Ratio
Input Noise Voltage
PSRR
eN
VS = ±3V to ±8V
RS = 100,
f = DC to 10Hz
25
25
Input Noise Current
Gain Bandwidth Product
iN
GBWP
f = 10Hz
25
25
Slew Rate
Rise Time
Overshoot
SR CL = 50pF, RL = 10k
tR
OS
25
25
25
Operating Supply Range
V+ to V-
25
Supply Current
ISUPP
No Load
25
0 to 70
Output Source Current
IO SOURCE
25
0 to 70
MIN TYP MAX UNITS
- ±0.7 ±5 µV
- ±1 ±8 µV
- 0.02 - µV/oC
- 100 - nV/month
- 4 10 pA
- 5 20 pA
- 8 20 pA
- 10 40
- 1012 -
pA
135 150
-
dB
130 -
- dB
±4.7 ±4.85
-
V
- ±4.95 -
V
-5 -5.2 to +4 3.5
V
-5 - 3.5 V
120 140
-
dB
120 -
- dB
120 140
-
dB
- 2 - µVP-P
- 0.01 - pA/Hz
- 2 - MHz
- 2.5 - V/µs
- 0.2 -
µs
- 20 -
%
4.5 - 16 V
- 2 3 mA
- - 3.2 mA
2.9 4.5 - mA
2.3 -
- mA
3


3Pages


7650SCB 電子部品, 半導体
INPUT
R1
- R2
+
OUTPUT
ICL7650S
INPUT
-
+
OUTPUT
FIGURE 1A. INVERTING AMPLIFIER
FIGURE 1B. FOLLOWER
R2
-
+
R1
OUTPUT
www.DataSheet4U.com
INPUT
NOTE: -R--R--1---1-+----R---R-2---2-
SHOULD BE LOW
IMPEDANCE FOR
OPTIMUM GUARDING
EXTERNAL
CAPACITORS
V+
OUTPUT
CRETN
6
7
8
1
5
4
2
3
V- GUARD
BOTTOM VIEW
FIGURE 1C. NON-INVERTING AMPLIFIER
FIGURE 1D. BOARD LAYOUT FOR INPUT GUARDING WITH
TO-99 PACKAGE
FIGURE 1. CONNECTION OF INPUT GUARDS
PIN COMPATIBILITY
The basic pinout of the 8-pin device corresponds, where
possible, to that of the industry standard 8-pin devices, the
LM741, LM101, etc. The null-storing external capacitors are
connected to pins 1 and 8, usually used for offset null or
compensation capacitors, or simply not connected. In the
case of the OP-05 and OP-07 devices, the replacement of
the offset-null pot, connected between pins 1 and 8 and V+,
by two capacitors from those pins to pin 5, will provide easy
compatibility. As for the LM108, replacement of the
compensation capacitor between pins 1 and 8 by the two
capacitors to pin 5 is all that is necessary. The same
operation, with the removal of any connection to pin 5, will
suffice for the LM101, µA748, and similar parts.
The 14-pin device pinout corresponds most closely to that of
the LM108 device, owing to the provision of “NC” pins for
guarding between the input and all other pins. Since this
device does not use any of the extra pins, and has no
provision for offset-nulling, but requires a compensation
capacitor, some changes will be required in layout to convert
it to the ICL7650S.
Typical Applications
Clearly the applications of the ICL7650S will mirror those of
other op amps. Anywhere that the performance of a circuit
can be significantly improved by a reduction of input-offset
voltage and bias current, the ICL7650S is the logical choice.
Basic non-inverting and inverting amplifier circuits are shown
in Figures 2 and 3. Both circuits can use the output clamping
circuit to enhance the overload recovery performance. The
only limitations on the replacement of other op amps by the
ICL7650S are the supply voltage (±8V Max) and the output
drive capability (10kload for full swing). Even these
limitations can be overcome using a simple booster circuit,
as shown in Figure 4, to enable the full output capabilities of
the LM741 (or any other standard device) to be combined
with the input capabilities of the ICL7650S. The pair form a
composite device, so loop gain stability, when the feedback
network is added, should be watched carefully.
0.1µF
0.1µF
INPUT
C
+
R
C
7650S
OUTPUT
-
CLAMP
R2
R3 + (R1||R2) 100k
For Full Clamp Effect
R3 R1
NOTE: R1||R2 indicates the parallel combination of R1 and R2.
FIGURE 2. NON INVERTING AMPLIFIER WITH OPTIONAL CLAMP
Figure 5 shows the use of the clamp circuit to advantage in a
zero-offset comparator. The usual problems in using a
chopper stabilized amplifier in this application are avoided,
since the clamp circuit forces the inverting input to follow the
input signal. The threshold input must tolerate the output
clamp current VlN/R without disturbing other portions of
the system.
The pin configuration of the 14 pin dual in-line package is
designed to facilitate guarding, since the pins adjacent to the
inputs are not used (this is different from the standard 741 and
101A pin configuration, but corresponds to that of the LM108).
6

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部品番号部品説明メーカ
7650SCB

ICL7650SCB

Intersil Corporation
Intersil Corporation


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