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UDA1350AH の電気的特性と機能

UDA1350AHのメーカーはNXP Semiconductorsです、この部品の機能は「IEC 958 audio DAC」です。


製品の詳細 ( Datasheet PDF )

部品番号 UDA1350AH
部品説明 IEC 958 audio DAC
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 




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UDA1350AH Datasheet, UDA1350AH PDF,ピン配置, 機能
INTEGRATED CIRCUITS
DATA SHEET
www.DataSheet4U.com
UDA1350AH
IEC 958 audio DAC
Preliminary specification
File under Integrated Circuits, IC01
1999 Dec 16

1 Page





UDA1350AH pdf, ピン配列
Philips Semiconductors
IEC 958 audio DAC
Preliminary specification
UDA1350AH
1 FEATURES
1.1 General
2.7 to 3.6 V power supply
Integrated digital filter and Digital-to-Analog Converter
(DAC)
www.DataSheet4MUa.csotmer-mode data output interface for off-chip sound
processing
256fs system clock output
20-bit data-path in interpolator
High performance
No analog post filtering required for DAC.
1.2 Control
Controlled either by means of static pins or via the
L3 microcontroller interface.
1.3 IEC 958 input
On-chip amplifier for converting IEC 958 input to CMOS
levels
Selectable IEC 958 input channel, one out of two
Lock indication signal available on pin LOCK
Lock indication signal combined on-chip with the Pulse
Code Modulation (PCM) status bit; in case non-PCM
has been detected pin LOCK indicates out-of-lock
Key channel-status bits available via L3 interface (lock,
pre-emphasis, audio sample frequency, two channel
PCM indication and clock accuracy).
1.4 Digital output and input interfaces
When the UDA1350AH is clock master of the data
output interface:
– BCKO and WSO signals are output
– I2S-bus or LSB-justified 16, 20 and 24 bits formats
are supported.
When the UDA1350AH is clock slave of the data input
interface:
– BCK and WS signals are input
– I2S-bus or LSB-justified 16, 20 and 24 bits formats
are supported.
1.5 Digital sound processing and DAC
Pre-emphasis information of IEC 958 input bitstream
available in L3 interface register and on pins
Automatic de-emphasis when using IEC 958 input with
32.0, 44.1 and 48.0 kHz audio sample frequencies
Soft mute by means of a cosine roll-off circuit selectable
via pin MUTE or the L3 interface
Interpolating filter (fs to 128fs) by means of a cascade of
a recursive filter and a FIR filter
Third-order noise shaper operating at 128fs generates
bitstream for the DAC
Filter stream digital-to-analog converter.
2 APPLICATIONS
Digital audio systems.
3 GENERAL DESCRIPTION
Available in two versions:
UDA1350AH:
– Full featured version in QFP44 package.
UDA1350ATS:
– Only IEC 958 input to DAC in SSOP28 package.
The UDA1350AH is a single chip IEC 958 audio decoder
with an integrated stereo digital-to-analog converter
employing bitstream conversion techniques.
1999 Dec 16
3


3Pages


UDA1350AH 電子部品, 半導体
Philips Semiconductors
IEC 958 audio DAC
7 PINNING
SYMBOL
RESET
VDDD(C)
VSSD
VSSD(C)
www.DataSheet4U.com
L3DATA
L3CLOCK
DATAI
BCKI
WSI
L3MODE
n.c.
MUTE
SELCHAN
n.c.
SPDIF0
SPDIF1
VDDA(DAC)
VOUTL
SELCLK
SELSPDIF
LOCK
VOUTR
TC
Vref
VSSA(DAC)
VSSA
VDDA
n.c.
CLKOUT
PREEM1
VSSA(PLL)
VDDA(PLL)
BCKO
TEST1
SELSTATIC
DATAO
WSO
n.c.
TEST2
n.c.
1999 Dec 16
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Preliminary specification
UDA1350AH
TYPE(1)
DISD
DS
DGND
DGND
DIOS
DIS
DISD
DISD
DISD
DIS
DID
DID
AI
AI
AS
AO
DID
DIU
DO
AO
DID
A
AGND
AGND
AS
DO
DO
AGND
AS
DO
DIU
DIU
DO
DO
DISD
DESCRIPTION
reset input
digital supply voltage for core
digital ground
digital ground for core
L3 interface data input and output
L3 interface clock input
I2S-bus data input
I2S-bus bit clock input
I2S-bus word select input
L3 interface mode input
not connected
mute control input
IEC 958 channel selection input
not connected
IEC 958 channel 0 input
IEC 958 channel 1 input
analog supply voltage for DAC
DAC left channel analog output
clock source for PLL selection input
IEC 958 data selection input
SPDIF and PLL lock indicator output
DAC right channel analog output
test pin; must be connected to digital ground (VSSD)
DAC reference voltage
analog ground for DAC
analog ground
analog supply voltage
not connected
clock output (256fs)
IEC 958 input pre-emphasis output 1
analog ground for PLL
analog supply voltage for PLL
I2S-bus bit clock output
test pin 1: must be connected to digital supply voltage (VDDD)
static pin control selection input
I2S-bus data output
I2S-bus word select output
not connected
test pin 2; must be connected to digital ground (VSSD)
not connected
6

6 Page



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共有リンク

Link :


部品番号部品説明メーカ
UDA1350AH

IEC 958 audio DAC

NXP Semiconductors
NXP Semiconductors
UDA1350ATS

IEC 958 audio DAC

NXP Semiconductors
NXP Semiconductors


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