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iT4005D の電気的特性と機能

iT4005DのメーカーはIterraです、この部品の機能は「12-Gb/s GaAs MMIC D flip-flop」です。


製品の詳細 ( Datasheet PDF )

部品番号 iT4005D
部品説明 12-Gb/s GaAs MMIC D flip-flop
メーカ Iterra
ロゴ Iterra ロゴ 




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iT4005D Datasheet, iT4005D PDF,ピン配置, 機能
iT4005D
12.5 Gb/s GaAs MMIC D Flip-Flop
(Advanced Information)
Description
www.DataSheet4U.com
Features
The iT4005D is a high-speed D-type flip flop fabricated using 1-μm HBT GaAs technology. Its
high output voltage, excellent rise and fall time and the high eye diagram quality at all clock
frequencies makes the iT4005D suitable for very high speed and complex digital applications
such as decision circuits, waveform shaping, register implementation, and timing adjustment.
The device consists of a master-slave latch designed using an ECL topology guarantee high-
speed operation. The data and clock inputs and data outputs are DC coupled. At the data input
port, the iT4005D tolerates a wide range of operating conditions, and the internal 50-ohm
resistors avoid the need for external terminations for impedance matching. The iT4005D uses
SCFL I/O levels and allows either single-ended or differential data input and output. For the
clock, a single-ended, DC-coupled input with an internal 50-ohm resistor followed by a DC block
is provided. An amplitude of 700 mV peak-to-peak for the clock is recommended, although
depending on the operating frequency, a lower amplitude may be usable. An on-chip output
buffer provides an excellent eye diagram at a 12.5 GHz clock frequency.
™ 2-13 GHz clock frequency range
™ 900 mVpp single ended output dynamic
™ Output rise time (20%-80%): 25 ps
™ Output fall time (20%-80%): 24 ps
™ DC coupled clock input
™ DC coupled data input
™ 50 ohm matched DC-coupled data output
™ Differential or single-ended inputs
™ Low power consumption:
1 W at -5.2 V (VQH = 0.0 V, VQL = -0.9 V)
0.7 W at -4.5 V (VQH = 0.0 V, VQL = -0.6 V)
0.5 W at -4.0 V (VQH = 0.0 V, VQL = -0.4 V)
Device
Diagram
www.iterrac.com
This is an Advanced data sheet. See “Product Status Definitions” on
Web site or catalog for product development status.
October 5, 2005 Doc. 4047 Rev 0
1
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938

1 Page





iT4005D pdf, ピン配列
iT4005D
12.5 Gb/s GaAs MMIC D Flip-Flop
(Advanced Information)
Electrical
Characteristics
1. Electrical
www.DataSheet4caUhm.acboraimecntet ristics at
temperature.
2. Minimum and
maximum values for
VDH and VDL have
to be set in order to
satisfy the following
rule: 0.2 V <(VDH -
VDL) <1 V
3. In case of single-
ended input, the
unused one must be
tied to Vindc which
must be nominally
set to the applied
input mean value.
4. Output change
state on input rising
edge.
5. Calculated as
follows in the
following equation:
PM[deg] = PM(measured) [ps]
BitDuration [ps]* 360 [ps]
where:
BitDuration[ps] =
1
BitRate[Gb/s]
6. Duty cycle 50%.
Asymmetrical duty
cycle may reduce
maximum frequency.
Symbol
Vee
VCLK
VCLKdc
VDH
VDL
Vinppd
Vindc
VQH
VQL
Tr
Tf
Tdl
Tdh
Ts
Th
PM1
PM2
FMAx
RMAx
RLin
RLout
Jpp
Jrms
Ic
Pd
Parameters
Min
Power supply voltage
Input clock voltage amplitude
Input clock voltage common mode
Data input voltage level, high level
(single ended) (2)
Data input voltage level, low level (single ended)
(2)
-5.45
0.5
-0.2
-0.6
-1
Data/clock input voltage level differential peak to
peak
DC input voltage (with DC-coupled input) (3)
Data output voltage amplidude high
Data output voltage amplidude low
Output rise time (20% - 80%)
Output fall time (20% - 80%)
Output fall delay (CLK vs. Q,Qb) (4)
Output rise delay (CLK vs. Q,Qb) (4)
0.50
-0.75
-0.05
-1.1
Minimum setup time
Minimum hold time
Phase margin at 12.5 Gb/s NRZ input (5)
Phase margin at 10.7 Gb/s NRZ input (5)
Clock frequency (6)
Input data rate (6)
Minimum input return loss (up to 13 GHz)
Minimum output return loss (up to 13 GHz)
Peak to peak jitter
RMS jitter
Power supply current
Power dissipation
2
2
Typ
-5.0
0.7
0
0.25
-0.25
1.0
0
0
-0.85
25
24
33
35
12
12
224
290
12.5
12.5
10
10
5
0.9
185
0.925
Max
-4.00
1.0
0.2
Units
V
V
V
0.6 V
0.6 V
2.0
0.25
0
-0.4
13
13
V
V
V
ps
ps
ps
ps
ps
ps
deg
deg
GHz
Gb/s
dB
dB
ps
ps
mA
W
www.iterrac.com
This is an Advanced data sheet. See “Product Status Definitions” on
Web site or catalog for product development status.
October 5, 2005 Doc. 4047 Rev 0
3
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938


3Pages


iT4005D 電子部品, 半導体
Recommended
Chip Mounting
www.DataSheet4U.com
iT4005D
12.5 Gb/s GaAs MMIC D Flip-Flop
(Advanced Information)
Pad Positions
And Chip
Dimensions
Chip size:
1600 μm ±10 μm x 2335 μm
±10 μm edge to edge
Chip thickness:
104 μm ±3 μm
Pad size:
100 μ m x 100 μm
RF pad pitch:
150 μm
Unlabeled pads are ground
and may be left floating
www.iterrac.com
This is an Advanced data sheet. See “Product Status Definitions” on
Web site or catalog for product development status.
October 5, 2005 Doc. 4047 Rev 0
6
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938

6 Page



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共有リンク

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部品番号部品説明メーカ
iT4005D

12-Gb/s GaAs MMIC D flip-flop

Iterra
Iterra


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