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iT4021DのメーカーはIterraです、この部品の機能は「T-type flip flop」です。 |
部品番号 | iT4021D |
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部品説明 | T-type flip flop | ||
メーカ | Iterra | ||
ロゴ | |||
このページの下部にプレビューとiT4021Dダウンロード(pdfファイル)リンクがあります。 Total 5 pages
iT4021D
20 Gb/s (12.5 Gb/s RZ) T-Type Flip-Flop
(Advanced Information)
Description
www.DataSheet4U.com
The iT4021D is a high-speed T-type flip-flop fabricated using 1µm HBT GaAs technology. The
T flip-flop consists of a master-slave latch, closed-in feedback, and is designed using an ECL
topology in order to guarantee high-speed operation. The data input may be either AC or DC
coupled, the output is DC coupled. At the input side the internal 50-ohm resistors avoid the
need for external terminations for impedance matching. The iT4021D uses SCFL I/O levels
and is designed to allow for either single-ended or differential data input/output. An on-chip,
output buffer produces an excellent eye diagram up to an output rate of 12.5 Gb/s rate (20
Gb/s NRZ or 12.5 Gb/s RZ input data rate) or 14 GHz input clock. The high output voltage,
excellent rise and fall times, and the high-quality eye diagram at all clock frequencies makes
the iT4021D suitable for very-high-speed, complex digital applications such as differential
encoding, clock dividers, and edge detectors.
Features
Data rate range: 20 NRZ (12.5 RZ) Gb/s
Maximum clock frequency as clock divider: 14 GHz
900 mVpp typical single-ended output
Input sensitivity: Single ended input >250 mV
Jitter transfer RMS: <1 ps
Output rise time (20% - 80%): <27 ps
Output fall time (20% - 80%): <24 ps
DC or AC coupled data input
50-ohm matched DC-coupled data output
Differential or single-ended inputs and
outputs
Full SCFL I/O level compatibility
Low power consumption: 0.71 W
Device
Diagram
Timing Diagram
www.iterrac.com
This is an Advanced data sheet. See “Product Status Definitions”
on Web site or catalog for product development status.
April 24, 2007 Doc. 4049 Rev 1.0
1
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938
1 Page iT4021D
20 Gb/s (12.5 Gb/s RZ) T-Type Flip-Flop
(Advanced Information)
Electrical
Characteristics
(cont.)
www.DataSheet4U.com
Symbol
RMAx
RLin
RLout
MPW
Jpp
Jrms
Ic
Pd
Parameters
Input data rate(4)
Minimum input return loss (up to 15 GHz)
Minimum output return loss (up to 15 GHz)
Minimum pulse width
Peak to peak jitter
RMS jitter
Power supply current
Power dissipation
Min Typ
Max Units
0 12.5 20 (-25) Gb/s
20 dB
5.5 dB
40 ps
78
9 ps
1.3 ps
136 mA
0.71 W
Eye Diagram
Performance
Die measurement
Vee: -5.2 V NRZ input rate: 12.5 Gb/s
Single-ended data input: +/-250 mVpp
Die measurement
Vee: -5.2 V + 5% = -4.95 V Clock: 12.5 GHz
Single-ended data input: +/-450 mVpp
www.iterrac.com
Test board measurement
VEE: -5.2 V RZ input rate: 12.5 Gb/s (duobinary precoder application)
Single-ended data input (0,-900 mVpp) DC coupled
Left: Time domain (fixed pattern) Right : Eye diagram (PN pattern)
Upper signal: RZ input Lower signal: Duobinary precoded output
For duobinary use TFF in single-ended input and tune Vindc on unused input.
This is an Advanced data sheet. See “Product Status Definitions”
on Web site or catalog for product development status.
April 24, 2007 Doc. 4049 Rev 1.0
3
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938
3Pages | |||
ページ | 合計 : 5 ページ | ||
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PDF ダウンロード | [ iT4021D データシート.PDF ] |
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
部品番号 | 部品説明 | メーカ |
iT4021D | T-type flip flop | Iterra |