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Número de pieza | iT4032D | |
Descripción | 50-ps wideband phase delay | |
Fabricantes | Iterra | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de iT4032D (archivo pdf) en la parte inferior de esta página. Total 6 Páginas | ||
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iT4032D
50-ps Wideband Phase Delay
With 180-deg. Flipper
(Advanced Information)
The iT4032D is an ultra-wideband phase delay fabricated using 0.1-μm HBT GaAs technology.
The high output voltage, excellent rise and fall times, and the high eye diagram quality at all
data rates up to 12.5 Gb/s makes the iT4032D suitable for timing adjustment in data and clock
distribution at a very high speed. Complex digital applications that can benefit from the iT4032D
include clock data recovery, edge detectors, NRZ/RZ converters, MUX/DEMUX, and data
restoration It is based on an ECL topology in order to guarantee high-speed operation. The
device features a single delay element that provides up to 50 ps delay and a 180 deg. shift
capability.
The delay control can be either differential (using both VCp and VCm) or single-ended (VCp is
the active control pad while VCm is shorted to VCref). The nominal control voltage range for
the delay is from -2.2 V to -3.0 V, whether the control is single-ended or differential. The
flipping control can be either differential (using both VFp and VFn), or single-ended (VFp is the
active control pad while VFm is shorted to VCref). The nominal control voltage for the flipping is
-2.2 V or -3.0 V whether the control is single-ended or differential. The device is capable of
delaying NRZ streams with a data rate up to 12.5 Gb/s or a clock signal with frequency up to
10.7 GHz. The inputs and the outputs are DC coupled. At the input side the internal 50-ohm
resistors avoid the need for external impedance matching terminations. The iT4032D uses
SCFL I/O levels and is designed so to allow for either single ended or differential data input.
Features
Wideband signal handling: up to 12.5 Gb/s NRZ
Delay adjustment: to 50 ps
Flipping capability (180 deg. shift)
900 mVpp typical single-ended output
Jitter RMS: <1.5 ps
Output rise time (20% – 80 %): <22 ps
Output fall time (20% – 80 %): <20 ps
50-ohm matched DC-coupled inputs and
outputs
Differential or single-ended I/O
Power consumption: 1.15 W
Device Diagram
www.iterrac.com
This is an Advanced data sheet. See “Product Status Definitions”
on Web site or catalog for product development status.
October 5, 2005 Doc. 4036 Rev 0
1
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938
1 page Recommended
Operational
Setup
www.DataSheet4U.com
Recommended
Chip Mounting
Chip size
2235 μm ±10 μm
x 1400 μm ±10 μm
Chip thickness: 104 μm
±3 μm
Pad size: 100 μm
x 100 μm
RF pad pitch: 150 μm
iT4032D
50-ps Wideband Phase Delay
With 180-deg. Flipper
(Advanced Information)
www.iterrac.com
This is an Advanced data sheet. See “Product Status Definitions”
on Web site or catalog for product development status.
October 5, 2005 Doc. 4036 Rev 0
5
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938
5 Page |
Páginas | Total 6 Páginas | |
PDF Descargar | [ Datasheet iT4032D.PDF ] |
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