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PDF iT4134D Data sheet ( Hoja de datos )

Número de pieza iT4134D
Descripción 2 to 4 GHz clock multiplier
Fabricantes Iterra 
Logotipo Iterra Logotipo



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No Preview Available ! iT4134D Hoja de datos, Descripción, Manual

iT4134D
X2, 4-to-7 GHz Clock Multiplier
(Advanced Information)
Description
www.DataSheet4U.com
The iT4134D is a high-speed X2 clock multiplier fabricated using 1-μm HBT GaAs technology
and employs an ECL topology to guarantee high-speed operation. It is an excellent choice for
digital clock multiplication, instrumentation, and edge detection. Digital clock multiplication is
implemented via XOR operation between the input clock and an internal delayed replica. Several
embedded electrically-controlled phase delays are also employed. Suitable regulation of the
phase delay voltage controls allows duty cycle control on the clock outputs. Suitable power
supply internal distribution provides the ability to disable the echo input which reduces power
consumption. The iT4134D can also be stimulated via NRZ data to perform edge detection. A
dedicated temperature monitoring pin is also provided.
Features
™ Clock input range: 4 to 7 GHz
™ 900 mVpp typical single-ended output
™ Input sensitivity: Single-ended input >200 mV
™ Jitter RMS <1 ps
™ 50-ohm matched inputs and outputs (DC)
™ Compatible SCFL I/O levels
™ Differential or single-ended I/O
™ Duty cycle control
™ Echo inputs available
™ Power consumption: 1.25 W
Device Diagram
Absolute
Maximum
Ratings
Stresses above those listed
under Absolute Maximum
Ratings may cause
permanent damage to the
device. This is a stress
rating only; functional
operation of the device at
these or any other
conditions above those
indicated in the operational
section of this document is
not implied. Exposure to
absolute maximum rating
conditions for extended
periods may affect device
reliability.
www.iterrac.com
Symbol
Parameters/conditions
Min.
Max. Units
VEE Power supply voltage
VPc
Phase delay voltage control (coarse duty cycle
adjustment)
-5.5 0 V
-3.5 0 V
VPf
Phase delay voltage control (fine duty cycle adjustment)
-3.5
0
V
VIH Data/clock input voltage level, high level
-1.2 1.2
V
VIL Data/clock input voltage level, low level
-1.2 1.2
V
TA Operating temperature range
TSTG
Storage temperature
-15 125 °C
-65 150 °C
This is an Advanced data sheet. See “Product Status Definitions”
on Web site or catalog for product development status.
October 10, 2005 Doc. 4056 Rev 0
1
iTerra Communications
2400 Geng Road, Ste. 100, Palo Alto, CA 94303
Phone (650) 424-1937, Fax (650) 424-1938

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