PDF IS61NVVP51236 Data sheet ( Hoja de datos )

Número de pieza	IS61NVVP51236
Descripción	(IS61NVVP25672 / IS61NVVP51236) STATE BUS SRAM
Fabricantes	ISSI
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No Preview Available ! IS61NVVP25672 IS61NVVP51236 ISSI® 256K x 72 and 512K x 36, 18Mb ADVANCE INFORMATION PIPELINE 'NO WAIT' STATE BUS SRAM JULY 2002 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle www.DataShee•t4UI.ncodmividual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 119-ball PBGA (x36) and 209-ball (x72) PBGA packages • Single +1.8V (± 5%) power supply • JTAG Boundary Scan • Industrial temperature available DESCRIPTION The 16 Meg 'NVVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. They are organized as 256K words by 72 bits, 512K words by 36 bits and are fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -250 -200 Units 2.6 3.2 ns 4 5 ns 250 200 MHz Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 1 1 page IS61NVVP25672 IS61NVVP51236 ISSI ® STATE DIAGRAM READ BEGIN READ DS READ READ WRITE DS WRITE BEGIN WRITE WRITE www.DataSheet4U.com READ BURST BURST BURST READ DESELECT BURST WRITE DS BURST DS WRITE DS READ BURST WRITE BURST SYNCHRONOUS TRUTH TABLE(1) Operation Address Used CS1 CS2 CS2 ADV WE BWx OE CKE CLK Not Selected Continue N/A X X X H X X X L ↑ Not Selected N/A H X X L X X X L ↑ Not Selected N/A X L X L X X X L ↑ Not Selected N/A X X H L X X X L ↑ Begin Burst Read External Address L H L L H X L L ↑ Continue Burst Read Next Address X X X H X X L L ↑ NOP/Dummy Read External Address L H L L H X H L ↑ Dummy Read Next Address X X X H X X H L ↑ Begin Burst Write External Address L H L L L L X L ↑ Continue Burst Write Next Address X X X H X L X L ↑ NOP/Write Abort N/A L H L L L H X L ↑ Write Abort Next Address X X X H X H X L ↑ Ignore Clock Current Address X X X X X X X H ↑ Notes: 1. "X" means don't care. 2. The rising edge of clock is symbolized by ↑ 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 5 5 Page IS61NVVP25672 IS61NVVP51236 ISSI ® READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter -250 Min. Max. -200 Min. Max. fmax Clock Frequency — 250 — 200 tKC Cycle Time 4.0 — 5— tKH Clock High Time 1.7 — 2— tKL Clock Low Time 1.7 — 2— tKQ Clock Access Time — 2.6 — 3.0 www.DataSheet4tUKQ.cXo(m2) Clock High to Output Invalid 0.8 — 1.5 — tKQLZ(2,3) Clock High to Output Low-Z 0.8 — 1— tKQHZ(2,3) Clock High to Output High-Z — 2.6 — 3.0 tOEQ Output Enable to Output Valid — 2.6 — 3.0 tOELZ(2,3) Output Enable to Output Low-Z 0— 0— tOEHZ(2,3) Output Disable to Output High-Z — 2.6 — 3.0 tAS Address Setup Time 1.0 — 1.2 — tWS Read/Write Setup Time 1.0 — 1.2 — tCES Chip Enable Setup Time 1.0 — 1.2 — tSE Clock Enable Setup Time 1.0 — 1.2 — tADVS Address Advance Setup Time 1.0 — 1.2 — tDS Data Setup Time 1.0 — 1.2 — tAH Address Hold Time 0.5 — 0.5 — tHE Clock EnableHold Time 0.5 — 0.5 — tWH Write Hold Time 0.5 — 0.5 — tCEH Chip Enable Hold Time 0.5 — 0.5 — tADVH Address Advance Hold Time 0.5 — 0.5 — tDH Data Hold Time 0.5 — 0.5 — tPDS ZZ High to Power Down —2 —2 tPUS ZZ Low to Power Down —2 —2 Notes: 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 ADVANCED INFORMATION Rev. 00A 07/17/02 11 11 Page

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