PDF IS61NLP25672 Data sheet ( Hoja de datos )

Número de pieza	IS61NLP25672
Descripción	(IS61NVPxxxxx) STATE BUS SRAM
Fabricantes	ISSI
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IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 256K x 72, 512K x 36 and 1M x 18 18Mb, PIPELINE 'NO WAIT' STATE BUS SRAM ISSI® JULY 2006 FEATURES www.DataSheet4U.com • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 209- ball (x72) PBGA packages • Power supply: NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) • JTAG Boundary Scan for PBGA packages • Industrial temperature available • Lead-free available DESCRIPTION The 18 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 72 bits, 512K words by 36 bits and 1M words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -250 -200 Units 2.6 3.1 ns 4 5 ns 250 200 MHz Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 1 1 page IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 ISSI ® PIN CONFIGURATION — 512K X 36, 165-Ball PBGA (TOP VIEW) 12345678 A NC B NC A CE BWc BWb CE2 CKE ADV A CE2 BWd BWa CLK WE OE C DQPc NC VDDQ VSS VSS VSS VSS VSS D DQc DQc VDDQ VDD VSS VSS VSS VDD E DQc DQc VDDQ VDD VSS VSS VSS VDD F DQc DQc VDDQ VDD VSS VSS VSS VDD G DQc DQc VDDQ VDD VSS VSS VSS VDD www.DataSheet4U.com H NC VDD NC VDD VSS VSS VSS VDD J DQd DQd VDDQ VDD VSS VSS VSS VDD K DQd DQd VDDQ VDD VSS VSS VSS VDD L DQd DQd VDDQ VDD VSS VSS VSS VDD M DQd DQd VDDQ VDD VSS VSS VSS VDD N DQPd NC VDDQ VSS NC NC NC VSS P NC NC A A TDI A1* TDO A R MODE NC A A TMS A0* TCK A 9 A A VDDQ VDDQ VDDQ VDDQ VDDQ NC VDDQ VDDQ VDDQ VDDQ VDDQ A A 10 11 A NC A NC NC DQPb DQb DQb DQb DQb DQb DQb DQb DQb NC ZZ DQa DQa DQa DQa DQa DQa DQa DQa NC DQPa A NC AA Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol Pin Name A Address Inputs A0, A1 Synchronous Burst Address Inputs ADV WE Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input CLK Synchronous Clock CKE Clock Enable CE, CE2, CE2 Synchronous Chip Enable BWx (x=a-d) Synchronous Byte Write Inputs OE Output Enable ZZ Power Sleep Mode MODE TCK, TDI TDO, TMS VDD NC DQx DQPx VDDQ VSS Burst Sequence Selection JTAG Pins 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 5 5 Page IS61NLP25672/IS61NVP25672 IS61NLP51236/IS61NVP51236 IS61NLP102418/IS61NVP102418 LINEAR BURST ADDRESS TABLE (MODE = VSS) 0,0 A1', A0' = 1,1 www.DataSheet4U.com 0,1 1,0 ISSI ® ABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Value Unit TSTG Storage Temperature –65 to +150 °C PD Power Dissipation 1.6 W IOUT Output Current (per I/O) 100 mA VIN, VOUT Voltage Relative to VSS for I/O Pins –0.5 to VDDQ + 0.3 V VIN Voltage Relative to VSS for for Address and Control Inputs –0.3 to 4.6 V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. OPERATING RANGE (IS61NLPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C OPERATING RANGE (IS61NVPx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C VDD 3.3V ± 5% 3.3V ± 5% VDDQ 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% VDD 2.5V ± 5% 2.5V ± 5% VDDQ 2.5V ± 5% 2.5V ± 5% Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. G 07/10/06 11 11 Page

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