PDF IS61NLP51218A Data sheet ( Hoja de datos )

Número de pieza	IS61NLP51218A
Descripción	(IS61NVPxxxxxA) STATE BUS SRAM
Fabricantes	ISSI
Logotipo
Hay una vista previa y un enlace de descarga de IS61NLP51218A (archivo pdf) en la parte inferior de esta página. Total 30 Páginas
No Preview Available ! IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO WAIT' STATE BUS SRAM ISSI® JUNE 2006 FEATURES www.DataSheet4U.com • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 165-ball PBGA and 119- ball PBGA packages • Power supply: NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%) NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%) • JTAG Boundary Scan for PBGA packages • Industrial temperature available • Lead-free available DESCRIPTION The 9 Meg 'NLP/NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 256K words by 36 bits and 512K words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -250 -200 Units 2.6 3.1 ns 4 5 ns 250 200 MHz Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/27/06 1 1 page IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A ISSI ® 119-PIN PBGA PACKAGE CONFIGURATION 256K x 36 (TOP VIEW) 1234567 A VDDQ A A NC A A VDDQ B NC CE2 A ADV A CE2 NC C NC A A VDD A A NC D DQc DQPc VSS NC Vss DQPb DQb E DQc DQc VSS CE Vss DQb DQb F VDDQ DQc VSS OE Vss DQb VDDQ www.DataSheet4U.com G DQc DQc BWc A BWb DQb DQb H DQc J VDDQ K DQd DQc VDD DQd VSS NC VSS WE VDD CLK Vss DQb DQb NC VDD VDDQ Vss DQa DQa L DQd DQd BWd NC BWa DQa DQa M VDDQ DQd VSS CKE Vss DQa VDDQ N DQd DQd VSS A1* Vss DQa DQa P DQd DQPd VSS A0* Vss DQPa DQa R NC A MODE VDD NC A NC T NC NC A A A NC ZZ U VDDQ TMS TDI TCK TDO NC VDDQ Note: A0 and A1 are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a-d) Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs OE ZZ MODE TCK, TDO TMS, TDI VDD VSS NC DQa-DQd DQPa-Pd VDDQ Output Enable Power Sleep Mode Burst Sequence Selection JTAG Pins Power Supply Ground No Connect Data Inputs/Outputs Parity Data I/O Output Power Supply Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/27/06 5 5 Page IS61NLP25636A/IS61NVP25636A IS61NLP51218A/IS61NVP51218A WRITE TRUTH TABLE (x36) Operation WE BWa BWb BWc BWd READ HXXXX WRITE BYTE a L LHHH WRITE BYTE b L H L HH WRITE BYTE c L HH L H WRITE BYTE d L HHH L WRITE ALL BYTEs LLLLL WRITE ABORT/NOP www.DataSheeNt4oUt.ecosm: L HHHH 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. ISSI ® INTERLEAVED BURST ADDRESS TABLE (MODE = VDD or NC) External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/27/06 11 11 Page

Páginas	Total 30 Páginas
PDF Descargar	[ Datasheet IS61NLP51218A.PDF ]

Hoja de datos destacado

Número de pieza	Descripción	Fabricantes
IS61NLP51218	256K x 32/ 256K x 36 and 512K x 18 PIPELINE NO WAIT STATE BUS SRAM	Integrated Silicon Solution Inc
IS61NLP51218A	(IS61NVPxxxxxA) STATE BUS SRAM	ISSI

Número de pieza	Descripción	Fabricantes
SLA6805M	High Voltage 3 phase Motor Driver IC.	Sanken
SDC1742	12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters.	Analog Devices

DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares,
permitiéndote verlos en linea o descargarlos en PDF.

DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar