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IS61NLP12836A の電気的特性と機能

IS61NLP12836AのメーカーはISSIです、この部品の機能は「(IS61NVPxxxxxA) STATE BUS SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 IS61NLP12836A
部品説明 (IS61NVPxxxxxA) STATE BUS SRAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS61NLP12836A Datasheet, IS61NLP12836A PDF,ピン配置, 機能
IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A
ISSI®
128K x 32, 128K x 36, and 256K x 18
4Mb, PIPELINE 'NO WAIT' STATE BUS SRAM
PRELIMINARY INFORMATION
SEPTEMBER 2005
FEATURES
www.DataSheet4U.com
• 100 percent bus utilization
• No wait cycles between Read and Write
• Internal self-timed write cycle
• Individual Byte Write Control
• Single R/W (Read/Write) control pin
• Clock controlled, registered address,
data and control
• Interleaved or linear burst sequence control using
MODE input
• Three chip enables for simple depth expansion
and address pipelining
• Power Down mode
• Common data inputs and data outputs
CKE pin to enable clock and suspend operation
• JEDEC 100-pin TQFP, 165-ball PBGA and 119-
ball PBGA packages
• Power supply:
NVP: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)
NLP: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)
• Industrial temperature available
• Lead-free available
DESCRIPTION
The 4 Meg 'NLP/NVP' product family feature high-speed,
low-power synchronous static RAMs designed to provide
a burstable, high-performance, 'no wait' state, device for
networking and communications applications. They are
organized as 128K words by 32 bits, 128K words by 36 bits,
and 256K words by 18 bits, fabricated with ISSI's advanced
CMOS technology.
Incorporating a 'no wait' state feature, wait cycles are
eliminated when the bus switches from read to write, or
write to read. This device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit.
All synchronous inputs pass through registers are controlled
by a positive-edge-triggered single clock input. Operations
may be suspended and all synchronous inputs ignored
when Clock Enable, CKE is HIGH. In this state the internal
device will hold their previous values.
All Read, Write and Deselect cycles are initiated by the
ADV input. When the ADV is HIGH the internal burst
counter is incremented. New external addresses can be
loaded when ADV is LOW.
Write cycles are internally self-timed and are initiated by
the rising edge of the clock inputs and when WE is LOW.
Separate byte enables allow individual bytes to be written.
A burst mode pin (MODE) defines the order of the burst
sequence. When tied HIGH, the interleaved burst sequence
is selected. When tied LOW, the linear burst sequence is
selected.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
Clock Access Time
Cycle Time
Frequency
-250 -200 Units
2.6 3.1 ns
4 5 ns
250 200 MHz
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability
arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any
published information and before placing orders for products.
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
09/12/05
1

1 Page





IS61NLP12836A pdf, ピン配列
IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A
ISSI®
www.DataSheet4U.com
Bottom View
119-Ball, 14 mm x 22 mm BGA
1 mm Ball Pitch, 7 x 17 Ball Array
Bottom View
165-Ball, 13 mm x 15mm BGA
1 mm Ball Pitch, 11 x 15 Ball Array
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
09/12/05
3


3Pages


IS61NLP12836A 電子部品, 半導体
IS61NLP12832A
IS61NLP12836A/IS61NVP12836A
IS61NLP25618A/IS61NVP25618A
ISSI®
165-PIN PBGA PACKAGE CONFIGURATION 256K x 18 (TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11
A NC
A
CE BWb NC CE2 CKE ADV NC A
A
B NC
A
CE2 NC BWa CLK WE OE
NC A NC
C NC NC VDDQ Vss
Vss Vss Vss Vss VDDQ NC DQPa
D NC DQb VDDQ VDD
Vss Vss
Vss VDD VDDQ NC DQa
E NC DQb VDDQ VDD
Vss Vss
Vss
VDD VDDQ
NC
DQa
www.DataShFeet4U.coNmC
G NC
DQb VDDQ VDD
DQb VDDQ VDD
H NC NC
NC VDD
Vss Vss Vss
Vss Vss Vss
Vss Vss Vss
VDD VDDQ NC DQa
VDD VDDQ NC DQa
VDD NC NC ZZ
J DQb NC VDDQ VDD
Vss Vss Vss VDD VDDQ DQa NC
K DQb NC VDDQ VDD
Vss Vss Vss VDD VDDQ DQa NC
L DQb NC VDDQ VDD
Vss Vss
Vss VDD VDDQ DQa NC
M DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa NC
N DQPb NC VDDQ Vss NC NC NC Vss VDDQ NC NC
P NC NC A A NC A1* NC A A A NC
R MODE NC A A NC A0* NC A A A A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
A Address Inputs
A0, A1
Synchronous Burst Address Inputs
ADV
WE
Synchronous Burst Address Advance/
Load
Synchronous Read/Write Control
Input
CLK Synchronous Clock
CKE
Clock Enable
CE, CE2, CE2 Synchronous Chip Enable
BWx (x=a,b) Synchronous Byte Write Inputs
OE Output Enable
ZZ Power Sleep Mode
MODE
VDD
NC
DQx
DQPx
VDDQ
VSS
Burst Sequence Selection
3.3V/2.5V Power Supply
No Connect
Data Inputs/Outputs
Parity Data I/O
Isolated output Power Supply
3.3V/2.5V
Ground
6 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774
Rev. 00C
09/12/05

6 Page



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部品番号部品説明メーカ
IS61NLP12836A

(IS61NVPxxxxxA) STATE BUS SRAM

ISSI
ISSI


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