PDF IS61NVP10018 Data sheet ( Hoja de datos )

Número de pieza	IS61NVP10018
Descripción	(IS61NVP10018 / IS61NVP51236) State Bus SRAM
Fabricantes	ISSI
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No Preview Available ! IS61NVP51236 IS61NVP10018 ISSI® 512K x 36 and 1M x 18 PRELIMINARY INFORMATION PIPELINE 'NO WAIT' STATE BUS SRAM SEPTEMBER 2002 FEATURES • 100 percent bus utilization • No wait cycles between Read and Write • Internal self-timed write cycle www.DataShee•t4UI.ncodmividual Byte Write Control • Single R/W (Read/Write) control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining for TQFP • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP, 119 PBGA package • VDD +2.5V power supply (± 5%) • VDDQ: 2.5V I/O Supply Voltage • Industrial temperature available DESCRIPTION The 18 Meg 'NVP' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for network and communications customers. They are organized as 524, 288 words by 36 bits and 1M words by 18 bits, fabricated with ISSI's advanced CMOS technology. Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence. When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. FAST ACCESS TIME Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -133 -166 Units 4.2 3.6 ns 7.5 6 ns 133 166 MHz Copyright © 2002 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-47744 Rev. 00A 09/06/02 1 1 page IS61NVP51236 IS61NVP10018 ISSI ® STATE DIAGRAM READ BEGIN READ DS READ READ WRITE DS WRITE BEGIN WRITE WRITE www.DataSheet4U.com READ BURST BURST BURST READ DESELECT BURST WRITE DS BURST DS WRITE DS READ BURST WRITE BURST SYNCHRONOUS TRUTH TABLE(1) Operation Address Used CE1 CE2 CE2 ADV WE BWx OE CKE CLK Not Selected N/A H X X L X X X L ↑ Not Selected N/A X L X L X X X L ↑ Not Selected N/A X X H L X X X L ↑ Not Selected Continue N/A X X X H X X X L ↑ Begin Burst Read External Address L H L L H X L L ↑ Continue Burst Read Next Address X X X H X X L L ↑ NOP/Dummy Read External Address L H L L H X H L ↑ Dummy Read Next Address X X X HX X H L ↑ Begin Burst Write External Address L H L L L L X L ↑ Continue Burst Write Next Address XXXHX LXL ↑ NOP/Write Abort N/A L H L L L H X L ↑ Write Abort Next Address XXXHXHX L ↑ Ignore Clock Current Address X X X X X X X H ↑ Notes: 1. "X" means don't care. 2. The rising edge of clock is symbolized by ↑ 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 09/06/02 5 5 Page IS61NVP51236 IS61NVP10018 SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SLEEP MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SLEEP current ZZ inactive to exit SLEEP current Conditions ZZ ≥ VIH www.DataSheet4U.com SLEEP MODE TIMING Min. 2 2 2 0 ISSI ® Max. 20 Unit mA cycle cycle cycle ns K ZZ Isupply All Inputs (except ZZ) tPDS ZZ setup cycle tZZI ISB2 Deselect or Read Only Outputs (Q) High-Z tPUS ZZ recovery cycle tRZZI Deselect or Read Only Normal operation cycle Don't Care Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. 00A 09/06/02 11 11 Page

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