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UT7R995 の電気的特性と機能

UT7R995のメーカーはAeroflex Circuit Technologyです、この部品の機能は「RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer」です。


製品の詳細 ( Datasheet PDF )

部品番号 UT7R995
部品説明 RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer
メーカ Aeroflex Circuit Technology
ロゴ Aeroflex Circuit Technology ロゴ 




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UT7R995 Datasheet, UT7R995 PDF,ピン配置, 機能
Standard Products
UT7R995 & UT7R995C RadClockTM
RadHard 2.5V/3.3V 200MHz High-Speed
Multi-phase PLL Clock Buffer
Datasheet
February, 2007
FEATURES:
+3.3V Core Power Supply
+2.5V or +3.3V Clock Output Power Supply
www.DataSheet4U- .Icnodmependent Clock Output Bank Power Supplies
Output frequency range: 6 MHz to 200 MHz
Bank pair output-output skew < 100 ps
Cycle-cycle jitter < 50 ps
50% ± 2% maximum output duty cycle at 100MHz
Eight LVTTL outputs with selectable drive strength
Selectable positive- or negative-edge synchronization
Selectable phase-locked loop (PLL) frequency range and
lock indicator
Phase adjustments in 625 to 1300 ps steps up to ± 7.8 ns
(1-6,8,10,12) x multiply and (1/2,1/4) x divide ratios
Compatible with Spread-Spectrum reference clocks
Power-down mode
Selectable reference input divider
Radiation performance
- Total-dose tolerance: 100 krad (Si)
- SEL Immune to a LET of 109 MeV-cm2/mg
- SEU Immune to a LET of 109 MeV-cm2/mg
Military temperature range: -55oC to +125oC
Extended industrial temp: -40oC to +125oC
Packaging options:
- 48-Lead Ceramic Flatpack
Standard Microcircuit Drawing: 5962-05214
- QML-Q and QML-V compliant part
INTRODUCTION:
The UT7R995/UT7R995C is a low-voltage, low-power, eight-
output, 6-to-200 MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high-performance microprocessor and communication sys-
tems.
The user programs both the frequency and the phase of the out-
put banks through nF[1:0] and DS[1:0] pins. The adjustable
phase feature allows the user to skew the outputs to lead or lag
the reference clock. Connect any one of the outputs to the
feedback input to achieve different reference frequency multi-
plication and division ratios.
The devices also feature split output bank power supplies that
enable banks 1 & 2, bank 3, and bank 4 to operate at a different
power supply levels. The ternary PE/HD pin controls the syn-
chronization of output signals to either the rising or the falling
edge of the reference clock and selects the drive strength of the
output buffers. The UT7R995 and UT7R995C both interface
to a digital clock while the UT7R995C will also interface to a
quartz crystal.
4F0
4F1
sOE
PD/DIV
PE/HD
VDD
VDDQ3
3Q1
3Q0
VSS
VSS
VDD
FB
VDD
VSS
VSS
2Q1
2Q0
VDDQ1
LOCK
VSS
DS0
DS1
1F0
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 40
10 39
11 UT7R995 38
12 & 37
13 UT7R995C 36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
3F1
3F0
FS
VSS
VSS
VDDQ4
4Q1
4Q0
VSS
VSS
VDD
XTAL1
NC/XTAL2
VDD
VSS
VSS
1Q1
1Q0
VDDQ1
VSS
TEST
2F1
2F0
1F1
Figure 1. 48-Lead Ceramic Flatpack Pin Description
1

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UT7R995 pdf, ピン配列
1.0 DEVICE CONFIGURATION:
The outputs of the UT7R995/C can be configured to run at fre-
quencies ranging from 6 MHz to 200 MHz. Each output bank
has the ability to run at separate frequencies and with various
phase skews. Furthermore, numerous clock division and multi-
plication options exist.
The following discussion and list of tables will summarize the
available configuration options for the UT7R995/C. Tables 1
through 12, are relevant to the following configuration discus-
sions.
Table 2: Reference Divider Settings (R-factor)
PD/DIV Operating Mode
Reference Input
Divider - (R)
LOW 1
Powered Down
Not Applicable
MID Normal Operation
2
HIGH
Normal Operation
1
Notes:
1. When PD/DIV = LOW, the device enters power-down mode.
w w w . TaDble 1a. Feet dbaack SDividher Seettiengs t(N-f4actoUr) . c o mIn addition to the reference and feedback dividers, the
Table 2. Reference Divider Settings (R-Factor)
UT7R995/C includes output dividers on Bank 3 and Bank 4,
Table 3. Output Divider Settings - Bank 3 (K-factor)
which are controlled by 3F[1:0] and 4F[1:0] as indicated in Ta-
Table 4. Output Divider Settings - Bank 4 (M-Factor)
bles 3 and 4, respectively.
Table 5. Frequency Divider Summary
Table 6. Calculating Output Frequency Settings
Table 7. Frequency Range Select
Table 3: Output Divider Settings - Bank 3 (K-factor)
Table 8. Multiplication Factor (MF) Calculation
3F(1:0)
Bank 3 Output Divider - (K)
Table 9. Signal Propagation Delays in Various Media
Table 10: Output Skew Settings
LL
2
Table 11. PE/HD Settings
HH 4
Table 12. Power Supply Constraints
Other 1
1
1.1 Divider Configuration Settings:
The feedback input divider is controlled by the 3-level DS[1:0]
pins as indicated in Table 1 and the reference input divider is
controlled by the 3-level PD/DIV pin as indicated in Table 2.
Although the Reference divider will continue to operate when
the UT7R995/C is in the standard TEST mode of operation, the
Feedback Divider will not be available.
Notes:
1. These states are used to program the phase of the respective banks. Please see
Equation 1 along with Tables 8 and 10.
Table 4: Output Divider Settings - Bank 4 (M-factor)
4F[1:0]
Bank 4 Output Divider (M)
LL 2
Table 1: Feedback Divider Settings (N-factor)
Other 1
1
DS[1:0]
Feedback Input
Divider - (N)
Permitted Output
Divider (K or M)
Connected to FB
Notes:
1. These states are used to program the phase of the respective banks. Please see
Equation 1 along with Tables 8 and 10.
LL 2
LM 3
LH 4
ML 5
MM 1
MH 6
HL 8
HM 10
HH 12
1 or 2
1
1, 2, or 4
1 or 2
1, 2, or 4
1 or 2
1 or 2
1
1
Each of the four divider options and their respective settings are
summarized in Table 5. By applying the divider options in Ta-
ble 5 to the calculations shown in Table 6, the user determines
the proper clock frequency for every output bank.
Table 5: Frequency Divider Summary
Division
Factors
Available Divider Settings
N 1, 2, 3, 4, 5, 6, 8, 10, 12
R 1, 2
K 1, 2, 4
M 1, 2
3


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UT7R995 電子部品, 半導体
When the outputs are configured for low drive operation, they
will provide a minimum 12mA of drive current regardless of
the selected output power supply. If the outputs are configured
for high drive operation, they will provide a minimum 24mA of
drive current under a 3.3V power supply and 20mA when pow-
ered from a 2.5V supply.
The UT7R995/C features split power supply buses for Banks 1
and 2, Bank 3, and Bank 4. These independent power supplies
enable the user to obtain both 3.3V and 2.5V output signals
from one UT7R995/C device. The core power supply (VDD)
must run from a 3.3V power supply. Table 12 summarizes the
various power supply options available with the UT7R995/C.
www.DataSheet4U.com Table 12: Power Supply Constraints 1
VDD
VDDQ1
VDDQ3
VDDQ4
3.3V 3.3V or 2.5V 3.3V or 2.5V 3.3V or 2.5V
Notes:
1. VDDQ1/3/4 must not be set at a level higher than that of VDD.
1.4 Reference Clock Interfaces
When an external, LVCMOS/LVTTL, digital clock is used to
drive the UT7R995 and UT7R995C, the reference clock signal
should drive the XTAL1 input of the RadClock, while the
XTAL2 output should be left unconnected (see Figure 4). Note,
for the UT7R995 only, the XTAL2 pin is defined as a no-
connect.
N/C
External
Digital
Oscillator
NC/XTAL2
XTAL1
VSS
Figure 4. External Digital Clock Oscillator Interface
In addition to a digital clock reference, the UT7R995C can in-
terface to a quartz crystal. When interfacing to a quartz crystal,
XTAL1 and XTAL2 are the input and output, respectively, of
an inverting amplifier within the RadClock. This inverting am-
plifier provides the initial 180o phase shift of the reference
clock whose frequency, and subsequent 180o phase shift, is set
by the quartz crystal and its surrounding RLC network. Figure
5 shows a typical pierce-oscillator with tank-circuit that will
support reliable startup of fundamental and odd-harmonic, AT-
cut, quartz crystals.
UT7R995C
XTAL1
Rdc
Y1
C2
XTAL2
R1
L1
C1
Cdc
Fundamental Frequency Pierce Crystal Oscillator
Rdc = ~10MΩ;
L1 = Not Used;
Cdc = Not Used
C2 is used to tune the circuit for stable oscillation.
Typical values for C2 range from 30pF to 50pF.
R1 and C1 are selected to create a time constant that facilitates the funda-
mental frequency (fF) of the quartz crystal as defined in equation 2.
Equation 2.
fF
=
(2π
1
* R1*C1)
As an example, selecting a value of 100Ω for R1 and 80pF for C1 would fa-
cilitate the reliable operation of a 20MHz, AT-cut, quartz crystal.
Higher Frequency Pierce Crystal Oscillator
Rdc = ~10MΩ;
Cdc = ~1.5nF;
C2 = Tuning capacitor
similar to prior example
R1 and C1 are selected to create a time constant that facilitates the overtone
frequency (fOT) of the quartz crystal as shown in equation 3.
Equation 3.
f OT
=
1
(2π * R1*C1)
Additionally, L1 is selected such that its relationship with C1 facilitates a
frequency falling between the fundamental frequency (fF) and the specified
overtone frequency (fOT) of the quartz crystal as shown in equation 4.
( )Equation 4.
fM
=
2π *
1
L1* C1
As an example, selecting the following component values will result in a
50MHz Pierce Crystal Oscillator based upon an 3rd overtone, AT-cut,
quartz crystal having a fundamental frequency of 16.6666MHz.
Rdc = 10MΩ;
R1 = 50Ω;
fF = 16.6666MHz;
Cdc = 1.5nF;
C1 = 55pF;
fOT = 50MHz
C2 = 30pF;
L1 = 300nH
Figure 5. Pierce Crystal Oscillator with Tank Circuit
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部品番号部品説明メーカ
UT7R995

RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer

Aeroflex Circuit Technology
Aeroflex Circuit Technology
UT7R995C

RadHard 2.5V/3.3V 200MHz High-Speed Multi-phase PLL Clock Buffer

Aeroflex Circuit Technology
Aeroflex Circuit Technology


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