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PDF PJSDA05C-5 Data sheet ( 特性 )

部品番号 PJSDA05C-5
部品説明 FIVE BI-DIRECTIONAL TVS ARRAY
メーカ Pan Jit International
ロゴ Pan Jit International ロゴ 

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PJSDA05C-5 Datasheet, PJSDA05C-5 PDF,ピン配置, 機能
PJSDA05C-5
FIVE BI-DIRECTIONAL TVS ARRAY FOR ESD PROTECTION
This Penta TVS Array has been designed to Protect Sensitive Equipment against
ESD and to prevent Latch-Up events in CMOS circuitry operating at 5Vdc and
below. This TVS array offers an integrated solution to protect up to 5 data lines
where the board space is a premium.
SPECIFICATION FEATURES
80W Power Dissipation (8/20µs Waveform)
Low Leakage Current, Maximum of 1µA @ 5Vdc
Very low Clamping voltage
IEC61000-4-2 ESD 15kV air, 8kV Contact Compliance
www.DataSheet4U.com
Industry standard SOT23-6L
100% Tin Matte Finish (RoHS Compliant)
6 54
APPLICATIONS
Video I/O ports protection
Set Top Boxes
Portable Instrumentation
1 23
SOT23-6L
Marking Code
616
MAXIMUM RATINGS
Rating
Peak Pulse Power (8/20µs Waveform)
Peak Pulse Current (8/20µs Waveform)
ESD Voltage (HBM)
Operating Temperature Range
Storage Temperature Range
Symbol
P pp
I pp
V ESD
TJ
Tstg
Value
80
5.0
>25
-55 to +150
-55 to +150
Units
W
A
kV
°C
°C
ELECTRICAL CHARACTERISTICS Tj = 25°C
Parameter
Reverse Stand-Off Voltage
Reverse Breakdown Voltage
Reverse Leakage Current
Clamping Voltage (8/20µs)
Clamping Voltage (8/20µs)
Off State Junction Capacitance
Off State Junction Capacitance
Symbol
VWRM
VBR
IR
Vc
Vc
Cj
Cj
Conditions
Min Typical Max
5.0
I BR =1mA
VR = 5V
I pp = 1A
I pp = 4A
0 Vdc Bias f = 1MHz
Between I/O pins and pin 2
5 Vdc Bias f = 1MHz
Between I/O pins and pin 2
6.2
8.0
1
12
15
15
7
Units
V
V
µA
V
V
pF
pF
7/28/2006
Page 1
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PJSDA05C-5

FIVE BI-DIRECTIONAL TVS ARRAY

Pan Jit International
Pan Jit International


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