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46V16M8 PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 46V16M8
部品説明 MT46V16M8
メーカ Micron Technology
ロゴ Micron Technology ロゴ 



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46V16M8 Datasheet, 46V16M8 PDF,ピン配置, 機能
DOUBLE DATA RATE
(DDR) SDRAM
FEATURES
• VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V
• Bidirectional data strobe (DQS) transmitted/
www.DataSheetr4eUc.ceoivmed with data, i.e., source-synchronous data
capture (x16 has two – one per byte)
• Internal, pipelined double-data-rate (DDR)
architecture; two data accesses per clock cycle
• Differential clock inputs (CK and CK#)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• DLL to align DQ and DQS transitions with CK
• Four internal banks for concurrent operation
• Data mask (DM) for masking write data (x16 has
two – one per byte)
• x16 has programmable IOL/IOH option
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• Longer lead TSOP for improved reliability (OCPL)
• 2.5V I/O (SSTL_2 compatible)
OPTIONS
• Configuration
32 Meg x 4 (8 Meg x 4 x 4 banks)
16 Meg x 8 (4 Meg x 8 x 4 banks)
8 Meg x 16 (2 Meg x 16 x 4 banks)
MARKING
32M4
16M8
8M16
• Plastic Package – OCPL
66-pin TSOP
(400 mil width, 0.65mm pin pitch)
TG
• Timing – Cycle Time
7.5ns @ CL = 2 (DDR266B)1
7.5ns @ CL = 2.5 (DDR266B)2
10ns @ CL = 2 (DDR200)3
-75Z
-75
-8
• Self Refresh
Standard
Low Power
none
L
NOTE: 1. Supports PC2100 modules with 2-3-3 timing
2. Supports PC2100 modules with 2.5-3-3 timing
3. Supports PC1600 modules with 2-2-2 timing
PRELIMINARY
128Mb: x4, x8, x16
DDR SDRAM
MT46V32M4 – 8 Meg x 4 x 4 banks
MT46V16M8 – 4 Meg x 8 x 4 banks
MT46V8M16 – 2 Meg x 16 x 4 banks
For the latest data sheet revisions, please refer to the Micron
Web site: www.micron.com/datasheets
PIN ASSIGNMENT (TOP VIEW)
66-Pin TSOP
x4 x8 x16
VDD
VDD
VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VssQ
NC NC DQ3
NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VssQ
NC NC DQ7
NC NC NC
VDDQ VDDQ VDDQ
NC NC LDQS
NC NC NC
VDD
VDD
VDD
NC DNU DNU
NC NC LDM
WE# WE# WE#
CAS# CAS# CAS#
RAS# RAS# RAS#
CS# CS# CS#
NC NC NC
BA0 BA0 BA0
BA1 BA1 BA1
A10/AP A10/AP A10/AP
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD
VDD
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
x16 x8
x4
66 VSS
VSS VSS
65 DQ15 DQ7 NC
64 VSSQ VSSQ VSSQ
63 DQ14 NC NC
62 DQ13 DQ6 DQ3
61 VDDQ VDDQ VDDQ
60 DQ12 NC NC
59 DQ11 DQ5 NC
58 VSSQ VSSQ VSSQ
57 DQ10 NC NC
56 DQ9 DQ4 DQ2
55 VDDQ VDDQ VDDQ
54 DQ8 NC NC
53 NC
NC NC
52 VSSQ VSSQ VSSQ
51 UDQS DQS DQS
50 DNU DNU DNU
49
VREF
VREF
VREF
48 VSS
VSS VSS
47 UDM DM DM
46 CK# CK# CK#
45 CK
CK CK
44 CKE CKE CKE
43 NC
NC NC
42 NC
NC NC
41 A11 A11 A11
40 A9
A9 A9
39 A8
A8 A8
38 A7
A7 A7
37 A6
A6 A6
36 A5
A5 A5
35 A4
A4 A4
34 VSS
VSS VSS
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
32 Meg x 4
8 Meg x 4 x 4 banks
4K
4K(A0–A11)
4 (BA0, BA1)
2K(A0–A9,A11)
16 Meg x 8
8 Meg x 16
4 Meg x 8 x 4 banks 2 Meg x 16 x 4 banks
4K 4K
4K(A0–A11)
4K(A0–A11)
4 (BA0, BA1)
4 (BA0, BA1)
1K(A0–A9)
512(A0–A8)
KEY TIMING PARAMETERS
SPEED
CLOCK RATE
DATA-OUT ACCESS DQS-DQ
GRADE CL = 2** CL = 2.5** WINDOW* WINDOW SKEW
-75Z 133 MHz
-75 100 MHz
-8 100 MHz
133 MHz
133 MHz
125 MHz
2.5ns
2.5ns
3.4ns
±0.75ns
±0.75ns
±0.8ns
+0.5ns
+0.5ns
+0.6ns
*Minimum clock rate @ CL = 2 (-75Z and -8) and CL = 2.5 (-75)
**CL = CAS (Read) Latency
128Mb: x4, x8, x16 DDR SDRAM
128Mx4x8x16DDR_C.p65 – Rev. C; Pub. 4/01
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2001, Micron Technology, Inc.
‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE
SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S
PRODUCTION DATA SHEET SPECIFICATIONS.

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