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5962-886700xxX PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 5962-886700xxX
部品説明 Electrically Erasable Industry Standard SPLD
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 



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5962-886700xxX Datasheet, 5962-886700xxX PDF,ピン配置, 機能
This is an abbreviated datasheet. Contact a Cypress repre-
sentative for complete specifications. For new designs,
please refer to the PALCE22V10
PALC22V10B
Reprogrammable CMOS PAL® Device
Features
• Advanced second generation PAL architecture
• Low power
— 90 mA max. standard
— 100 mA max. military
• CMOS EPROM technology for reprogrammability
• Variable product terms
www.DataSheet4U.co2mx (8 through 16) product terms
• User-programmable macrocell
— Output polarity control
— Individually selectable for registered or combinato-
rial operation
— 15 ns commercial and industrial
10 ns tCO
10 ns tS
15 ns tPD
50 MHz
— 15 ns and “20 ns” military
10/15 ns tCO
10/17 ns tS
15/20 ns tPD
50/31 MHz
• Up to 22 input terms and 10 outputs
• Enhanced test features
— Phantom array
— Top test
— Bottom test
— Preload
• High reliability
— Proven EPROM technology
— 100% programming and functional testing
• Windowed DIP, windowed LCC, DIP, LCC, PLCC avail-
able
Functional Description
The Cypress PALC22V10B is a CMOS second-generation
programmable logic array device. It is implemented with the
familiar sum-of-products (AND-OR) logic structure and a new
concept, the Programmable Macrocell.
The PALC22V10B is executed in a 24-pin 300-mil molded DIP,
a 300-mil windowed cerDIP, a 28-lead square ceramic lead-
less chip carrier, a 28-lead square plastic leaded chip carrier,
and provides up to 22 inputs and 10 outputs. When the win-
dowed cerDIP is exposed to UV light, the 22V10B is erased
and can then be reprogrammed. The programmable macrocell
provides the capability of defining the architecture of each out-
put individually. Each of the 10 potential outputs may be spec-
ified as registeredor combinatorial.Polarity of each output
may also be individually
Logic Block Diagram (PDIP/CDIP)
VSS I I I I I I I I I I CP/I
12 11 10 9 8 7 6 5 4 3 2 1
8 10
12 14
PROGRAMMABLE
ANDARRAY
(132X 44)
16 16
14
12 10
8
Reset
Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Macrocell Preset
13 14 15 16 17 18 19
20 21 22 23 24
I
I/O9 I/O8 I/O7 I/O6
I/O5 I/O4
I/O3 I/O2 I/O1 I/O0 VCC
V10B1
Cypress Semiconductor Corporation 3901 North First Street San Jose CA 95134 408-943-2600
Document #: 38-03018 Rev. **
Revised March 6, 1997

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