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PDF APL5912 Data sheet ( Hoja de datos )
| Número de pieza | APL5912 | |
| Descripción | 0.8V Reference Ultra Low Dropout Linear Regulator | |
| Fabricantes | Anpec Electronics | |
| Logotipo |  |
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APL5912
0.8V Reference Ultra Low Dropout (0.2V@5A) Linear Regulator
Features
General Description
• Ultra Low Dropout
- 0.2V (typical) at 5A Output Current
www.DataSheet4U•.com Low ESR Output Capacitor (Multi-layer Chip
Capacitors (MLCC)) Applicable
• 0.8V Reference Voltage
• High Output Accuracy
- ±1.5% over Line, Load and Temperature
• Fast Transient Response
• Adjustable Output Voltage by External
Resistors
• Power-On-Reset Monitoring on Both VCNTL
and VIN Pins
• Internal Soft-Start
• Current-Limit Protection
• Under-Voltage Protection
• Thermal Shutdown with Hysteresis
• Power-OK Output with a Delay Time
• Shutdown for Standby or Suspend Mode
• Simple SOP-8-P Package with Exposed Pad
• Lead Free Available (RoHS Compliant)
The APL5912 is a 5A ultra low dropout linear regulator.
This product is specifically designed to provide well
supply voltage for front-side-bus termination on
motherboard and NB applications. The IC needs two
supply voltages, a control voltage for the circuitry and
a main supply volatege for power conversion, to reduce
power dissipation and provide extremely low dropout.
The APL5912 integrates many functions. A Power-On-
Reset (POR) circuit monitors both supply voltages to
prevent wrong operations. A thermal shutdown and
current limit functions protect the device against
thermal and current over-loads. A POK indicates the
output status with time delay which is set internally. It
can control other converter for power sequence. The
APL5912 can be enabled by other power system.
Pulling and holding the EN pin below 0.3V shuts off
the output.
The APL5912 is available in SOP-8-P package which
features small size as SOP-8 and an Exposed Pad to
reduce the junction-to-case resistance, being applicable
in 2~3W applications.
Pin Configuration
Applications
• Front Side Bus VTT (1.2V/5A)
• Note Book PC Applications
• Motherboard Applications
GND 1
8 EN
FB 2
VOUT 3
VIN
7 POK
6 VCNTL
VOUT 4
5 VIN
SOP-8-P (Top View)
= Exposed Pad
(connected to VIN plane for better heat
dissipation)
Copyright © ANPEC Electronics Corp.
Rev. A.6 - Jun., 2005
1
www.anpec.com.tw
1 page  
APL5912
Electrical Characteristics (Cont.)
Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and TA = 0
to 70°C, unless otherwise specified. Typical values refer to TA = 25°C.
Symbol
Parameter
www.DataSheet4UO.coUmTPUT VOLTAGE
VREF Reference Voltage
Output Voltage Accuracy
Test Conditions
FB =VOUT
IOUT=0A ~ 5A, TJ= -25 ~125oC
APL5912
Unit
Min Typ Max
0.8 V
-1.5 +1.5 %
Line Regulation
VCNTL=3.3 ~ 5V
0.06 0.15 %
Load Regulation
IOUT=0A ~ 5A
0.06 0.15 %
DROPOUT VOLTAGE
Dropout Voltage
PROTECTION
ILIM Current Limit
TSD Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
Under-Voltage Threshold
ENABLE and SOFT-START
IOUT = 5A, VCNTL=5V, TJ= 25oC
IOUT = 5A, VCNTL=5V, TJ= -25~125oC
VCNTL=5V, TJ= 25oC
VCNTL=5V, TJ= -25 ~ 125oC
VCNTL=3.3V, TJ= 25oC
VCNTL=3.3V, TJ= -25 ~ 125oC
TJ Rising
VFB Falling
7
6
6.8
6
0.15 0.2
0.25
89
7.8 8.8
150
50
0.4
V
V
A
A
A
A
oC
oC
V
EN Logic High Threshold Voltage VEN Rising
0.3 0.4 0.5 V
EN Hysteresis
EN Pin Pull-Up Current
TSS Soft-Start Interval
POWER OK and DELAY
VPOK
VPNOK
POK Threshold Voltage for
Power OK
POK Threshold Voltage for
Power Not OK
POK Low Voltage
TDELAY POK Delay Time
EN=GND
VFB Rising
VFB Falling
POK sinks 5mA
30 mV
10 µA
2 mS
90% 92% 94% VREF
79% 81% 83% VREF
0.25 0.4 V
1 3 10 mS
Copyright © ANPEC Electronics Corp.
Rev. A.6 - Jun., 2005
5
www.anpec.com.tw
5 Page 
APL5912
Functional Pin Description
GND (Pin 1)
Ground pin of the circuitry. All voltage levels are measured
with respect to this pin.
FB (Pin 2)
www.DataSheet4UC.coonmnecting this pin to an external resistor divider
receives the feedback voltage of the regulator. The
output voltage set by the resistor divider is determined
by : VOUT = 0.8 ⋅ 1 + R1
R2
(V)
where R1 is connected from VOUT to FB with Kelvin
sensing and R2 is connected from FB to GND. A
bypass capacitor may be connected with R1in parallel
to improve load transient response. The recommended
R2 and R1 are in the range of 100~10kΩ.
VOUT (Pin 3,4)
for the main supply voltage. Please tie the Exposed
Pad and VIN Pin (Pin 8) together to reduce the dropout
voltage. The voltage at thispins ismonitored for Power-
On Reset purpose.
VCNTL (Pin 6)
Power input pin of the control circuitry. Connecting
this pin to a +5V (recommended) supply voltage
provides the bias for the control circuitry. The voltage
at this pin is monitored for Power-On Reset purpose.
POK (Pin 7)
Power-OK signal output pin. This pin is an open-drain
output used to indicate status of output voltage by
sensing FB voltage. This pin is pulled low when the
rising FB voltage is not above the VPOK threshold or
the falling FB voltage is below the VPNOK threshold,
indicating the output is not OK.
Output of the regulator. Please connect Pin 3 and 4
together using wide tracks. It is necessary to connect
a output capacitor with this pin for closed-loop
compensation and improving transient responses.
VIN (Pin 5) and Exposed Pad
Main supply input pins for power conversions. The
Exposed Pad provide a very low impedance input path
EN (Pin 8)
Enable control pin. Pulling and holding this pin below
0.3V shuts down the output. When re-enabled, the IC
undergoes a new soft-start cycle . Left this pin open,
an internal current source 10µA pulls this pin up to
VCNTL voltage, enabling the regulator.
Functional Description
Power-On-Reset
Internal Soft-Start
A Power-On-Reset (POR) circuit monitors both input
voltages at VCNTL and VIN pins to prevent wrong logic
controls. The POR function initiates a soft-start
process after the two supply voltages exceed their
rising POR threshold voltages during powering on. The
POR function also pulls low the POK pin regardless
the output voltage when the VCNTL voltage falls be-
low it’s falling POR threshold.
An internal soft-start function controls rise rate of the
output voltage to limit the current surge at start-up.
The typical soft-start interval is about 2mS.
Output Voltage Regulation
Anerroramplifierworking withatemperature-compensated
0.8V reference and an output NMOS regulates output
to the preset voltage. The error amplifier designed with
Copyright © ANPEC Electronics Corp.
Rev. A.6 - Jun., 2005
11
www.anpec.com.tw
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet APL5912.PDF ] | |
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