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PDF AT25F1024A Data sheet ( Hoja de datos )
| Número de pieza | AT25F1024A | |
| Descripción | SPI Serial Memory | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
– Datasheet Describes Mode 0 Operation
• 20 MHz Clock Rate
• Byte Mode and 256-byte Page Mode for Program Operations
• Sector Architecture:
– Four Sectors with 32K Bytes Each (1M)
– 128 Pages per Sector
• Product Identification Mode
• Low-voltage Operation
– 2.7 (VCC = 2.7V to 3.6V)
• Sector Write Protection
• Write Protect (WP) Pin and Write Disable Instructions for
www.DataShbeoett4hUH.caormdware and Software Data Protection
• Self-timed Program Cycle (20 µs/Byte Typical)
• Self-timed Sector Erase Cycle (1 second/Sector Typical)
• Single Cycle Reprogramming (Erase and Program) for Status Register
• High Reliability
– Endurance: 10,000 Write Cycles Typical
• Lead-free/Halogen-free Devices
• 8-lead JEDEC SOIC and 8-lead SAP Packages
Description
The AT25F1024A provides 1,048,576 bits of serial reprogrammable Flash memory
organized as 131,072 words of 8 bits each. The device is optimized for use in many
industrial and commercial applications where low-power and low-voltage operation
are essential. The AT25F1024A is available in a space-saving 8-lead JEDEC SOIC
and 8-lead SAP packages.
The AT25F1024A is enabled through the Chip Select pin (CS) and accessed via a 3-
wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial
Clock (SCK). All write cycles are completely self-timed.
BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array is enabled by
programming the status register. Separate write enable and write disable instructions
are provided for additional data protection. Hardware data protection is provided via
the WP pin to protect against inadvertent write attempts to the status register. The
HOLD pin may be used to suspend any serial communication without resetting the
serial sequence.
Pin Configurations
8-lead SOIC
Pin Name
CS
SCK
Function
Chip Select
Serial Data Clock
CS
SO
WP
GND
1
2
3
4
8 VCC
7 HOLD
6 SCK
5 SI
SI Serial Data Input
SO
GND
VCC
WP
HOLD
Serial Data Output
Ground
Power Supply
Write Protect
Suspends Serial Input
8-lead SAP
VCC 8
HOLD 7
SCK 6
SI 5
1 CS
2 SO
3 WP
4 GND
Bottom View
SPI Serial
Memory
1M (131,072 x 8)
AT25F1024A
Advance
Information
Rev. 3346C–SEEPR–7/04
1
1 page  
Serial Interface
Description
www.DataSheet4U.com
MASTER: The device that generates the serial clock.
SLAVE: Because the Serial Clock pin (SCK) is always an input, the AT25F1024A
always operates as a slave.
TRANSMITTER/RECEIVER: The AT25F1024A has separate pins designated for data
transmission (SO) and reception (SI).
MSB: The Most Significant Bit (MSB) is the first bit transmitted and received.
SERIAL OP-CODE: After the device is selected with CS going low, the first byte will be
received. This byte contains the op-code that defines the operations to be performed.
INVALID OP-CODE: If an invalid op-code is received, no data will be shifted into the
AT25F1024A, and the serial output pin (SO) will remain in a high impedance state until
the falling edge of CS is detected again. This will reinitialize the serial communication.
CHIP SELECT: The AT25F1024A is selected when the CS pin is low. When the device
is not selected, data will not be accepted via the SI pin, and the serial output pin (SO)
will remain in a high impedance state.
HOLD: The HOLD pin is used in conjunction with the CS pin to select the AT25F1024A.
When the device is selected and a serial sequence is underway, HOLD can be used to
pause the serial communication with the master device without resetting the serial
sequence. To pause, the HOLD pin must be brought low while the SCK pin is low. To
resume serial communication, the HOLD pin is brought high while the SCK pin is low
(SCK may still toggle during HOLD). Inputs to the SI pin will be ignored while the SO pin
is in the high impedance state.
WRITE PROTECT: The AT25F1024A has a write lockout feature that can be activated
by asserting the write protect pin (WP). When the lockout feature is activated, locked-out
sectors will be READ only. The write protect pin will allow normal read/write operations
when held high. When the WP is brought low and WPEN bit is “1”, all write operations to
the status register are inhibited. WP going low while CS is still low will interrupt a write to
the status register. If the internal status register write cycle has already been initiated,
WP going low will have no effect on any write operation to the status register. The WP
pin function is blocked when the WPEN bit in the status register is “0”. This will allow the
user to install the AT25F1024A in a system with the WP pin tied to ground and still be
able to write to the status register. All WP pin functions are enabled when the WPEN bit
is set to “1”.
3346C–SEEPR–7/04
5
5 Page 
Timing Diagrams (for SPI Mode 0 (0, 0))
Synchronous Data Timing
CS
SCK
VIH
VIL
tCSS
VIH
VIL
www.DataSheet4U.com
SI
VIH
VIL
VOH
SO
VOL
HI-Z
tWH
tSU
VALID IN
tH
tWL
tV
WREN Timing
tCS
tCSH
tHO tDIS
HI-Z
WRDI Timing
3346C–SEEPR–7/04
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AT25F1024A.PDF ] | |
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