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E5108ASE の電気的特性と機能

E5108ASEのメーカーはElpida Memoryです、この部品の機能は「 EDE5108ASE」です。


製品の詳細 ( Datasheet PDF )

部品番号 E5108ASE
部品説明 EDE5108ASE
メーカ Elpida Memory
ロゴ Elpida Memory ロゴ 




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E5108ASE Datasheet, E5108ASE PDF,ピン配置, 機能
PRELIMINARY DATA SHEET
512M bits DDR2 SDRAM
EDE5104AGSE (128M words × 4 bits)
EDE5108AGSE (64M words × 8 bits)
Description
The EDE5104AGSE is a 512M bits DDR2 SDRAM
organized as 33,554,432 words × 4 bits × 4 banks.
The EDE5108AGSE is a 512M bits DDR2 SDRAM
www.DataSheet4Uo.crogmanized as 16,777,216 words × 8 bits × 4 banks.
They are packaged in 60-ball FBGA (µBGA) package.
Features
Power supply: VDD, VDDQ = 1.8V ± 0.1V
Double-data-rate architecture: two data transfers per
clock cycle
Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
DLL aligns DQ and DQS transitions with CK
transitions
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Four internal banks for concurrent operation
Data mask (DM) for write data
Burst lengths: 4, 8
/CAS Latency (CL): 3, 4, 5
Auto precharge operation for each burst access
Auto refresh and self refresh modes
Average refresh period
7.8µs at 0°C TC ≤ +85°C
3.9µs at +85°C < TC ≤ +95°C
SSTL_18 compatible I/O
Posted CAS by programmable additive latency for
better command and data bus efficiency
Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
/DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
FBGA (µBGA) package with lead free solder
(Sn-Ag-Cu)
RoHS compliant
Document No. E0715E20 (Ver. 2.0)
Date Published July 2005 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2005

1 Page





E5108ASE pdf, ピン配列
EDE5104AGSE, EDE5108AGSE
Pin Configurations
/xxx indicates active low signal.
60-ball FBGA (µBGA)
www.DataSheet4U.com
1 23
A
VDD NU/ /RDQS VSS
(NC)*
B
DQ6
(NC)*
VSSQ
DM/RDQS
(DM)*
C
VDDQ DQ1 VDDQ
D
DQ4
(NC)*
VSSQ
DQ3
E
VDDL VREF VSS
F
CKE /WE
G
NC BA0 BA1
H
A10 A1
J
VSS A3
A5
K
A7 A9
L
VDD A12 NC
789
VSSQ /DQS VDDQ
DQS
VSSQ
DQ7
(NC)*
VDDQ DQ0 VDDQ
DQ2
VSSQ
DQ5
(NC)*
VSSDL CK VDD
/RAS /CK ODT
/CAS /CS
A2 A0 VDD
A6 A4
A11 A8 VSS
NC A13
(Top view)
Note: ( )* marked pins are for ×4 organization.
Pin name
Function
A0 to A13
Address inputs
BA0, BA1
Bank select
DQ0 to DQ15
Data input/output
DQS, /DQS
Differential data strobe
RDQS, /RDQS
Differential data strobe for read
/CS Chip select
/RAS, /CAS, /WE
Command input
CKE
Clock enable
CK, /CK
Differential clock input
DM Write data mask
Notes: 1. Not internally connected with die.
2. Don’t use other than reserved functions.
Pin name
ODT
VDD
VSS
VDDQ
VSSQ
VREF
VDDL
VSSDL
NC*1
NU*2
Function
ODT control
Supply voltage for internal circuit
Ground for internal circuit
Supply voltage for DQ circuit
Ground for DQ circuit
Input reference voltage
Supply voltage for DLL circuit
Ground for DLL circuit
No connection
Not usable
Preliminary Data Sheet E0715E20 (Ver. 2.0)
3


3Pages


E5108ASE 電子部品, 半導体
EDE5104AGSE, EDE5108AGSE
Recommended DC Operating Conditions (SSTL_18)
Parameter
Symbol
min.
typ. max.
Unit Notes
Supply voltage
VDD
1.7
1.8 1.9
V4
Supply voltage for output
VDDQ
1.7
1.8 1.9
V4
Input reference voltage
VREF
0.49 × VDDQ
0.50 × VDDQ 0.51 × VDDQ
V
1, 2
Termination voltage
VTT
VREF 0.04
VREF
VREF + 0.04
V
3
DC input logic high
VIH (DC)
VREF + 0.125
VDDQ + 0.3
V
DC input low
AC input logic high
-6C, -6E
-5C, -4A
www.DataSheet4UA.cCominput low
-6C, -6E
-5C, -4A
VIL (DC)
VIH (AC)
VIH (AC)
VIL (AC)
VIL (AC)
0.3
VREF + 0.200
VREF + 0.250
VREF – 0.125
VREF 0.200
VREF 0.250
V
V
V
V
V
Notes: 1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically
the value of VREF is expected to be about 0.5 × VDDQ of the transmitting device and VREF are expected
to track variations in VDDQ.
2. Peak to peak AC noise on VREF may not exceed ±2% VREF (DC).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and
VDDL tied together.
Preliminary Data Sheet E0715E20 (Ver. 2.0)
6

6 Page



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共有リンク

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部品番号部品説明メーカ
E5108ASE

EDE5108ASE

Elpida Memory
Elpida Memory


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