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PDF MT28C128564W30D Data sheet ( Hoja de datos )
| Número de pieza | MT28C128564W30D | |
| Descripción | (MT28C128532W18 / MT28C128564W18) 128Mb Multibank Burst Flash 32Mb ASYNC/PAGE CellularRAM COMBO Memory | |
| Fabricantes | Micron Technology | |
| Logotipo |  |
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ADVANCE‡
128Mb MULTIBANK BURST FLASH
32Mb/64Mb ASYNC/PAGE CellularRAM COMBO
FLASH AND CellularRAM™
COMBO MEMORY
MT28C128532W18/W30D
MT28C128564W18/W30D
Low Voltage, Wireless Temperature
Features
• Stacked die Combo package
Includes two 64Mb Flash devices
Choice of either one 32Mb or one 64Mb
www.DataSheet4U.cCoemllularRAMÔ device
• Basic configuration
Flash
Flexible multibank architecture
4 Meg x 16 Async/Page/Burst interface
Support for true concurrent operations with
no latency
CellularRAM
Low-power, high-density design
2 Meg x 16 or 4 Meg x 16 configurations
Async/Page
• F_VCC, VCCQ, F_VPP, PS_VCC voltages
1.70V (MIN)/1.95V (MAX) F_VCC, PS_VCC
1.70V (MIN)/2.24V (MAX) VCCQ (W18)
1.70V (MIN)/3.3V(MAX) VCCQ (W30)
1.80V (TYP) F_VPP (in-system PROGRAM/ERASE)
12V ±5% (HV) F_VPP (in-house programming and
accelerated programming algorithm [APA]
activation)
• Asynchronous access time
Flash/CellularRAM access time: 60ns @ 1.70V VCC
• Page Mode read access (W18/W30)
Interpage read access: 60ns @ 1.70V F_VCC , PS_VCC (W18)
Intrapage read access: 20ns @ 1.70V F_VCC, PS_VCC (W18)
Interpage read access: 70ns @ 1.70V F_VCC , PS_VCC (W30)
Intrapage read access: 22ns @ 1.70V F_VCC, PS_VCC (W30)
• Enhanced suspend options
ERASE-SUSPEND-to-READ within same bank
PROGRAM-SUSPEND-to-READ within same bank
ERASE-SUSPEND-to-PROGRAM within same bank
• Read/Write CellularRAM during program/erase of
Flash
• Each Flash contains two 64-bit chip protection
registers for security purposes
• Flash PROGRAM/ERASE cycles
100,000 WRITE/ERASE cycles per block
• Cross-compatible command set support
Extended command set
Common Flash interface (CFI) compliant
• Manufacturer’s ID (ManID)
Micron® (0x2Ch)
Intel® (0x89h)
Figure 1: 77-Ball FBGA
1
A A4
234567
A18 A19 PS_VSS F_VCC F_VCC A21
8
A11
B A5 PS_LB#
PS_VSS NC CLK NC A12
C A3
A17
F_VPP PS_WE# PS_CE# A9
A13
D A2
A7
F_WP# ADV# A20 A10 A15
E A1
A6 PS_UB# F_RST# F_WE# A8
A14 A16
F A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT# F_CE2#
G PS_OE# DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 F_OE2#
H NC F_OE1# DQ9 DQ11 DQ4 DQ6 DQ15 VCCQ
J F_CE1# NC NC NC PS_VCC F_VCC VCCQ PS_ZZ#
K PS_VSS VSSQ VCCQ F_VCC PS_VSS VSSQ F_VSS PS_VSS
Top View
(Ball Down)
Options
• Timing
60ns
70ns
• Burst Frequency
66 MHz1
54 MHz
• Boot Block Configuration
Top/Top
Top/Bottom
Bottom/Top
Bottom/Bottom
• I/O Voltage Range
VccQ 1.70V–1.95V
VccQ 1.70V–3.3V
• Manufacturer’s ID (ManID)
Micron (0x2Ch)
Intel (0x89h)
• Operating Temperature Range
Wireless Temperature (-25°C to +85°C)
• Package
77-ball FBGA (8 x 10 grid)
Marking
-60
-70
6
5
TT
TB
BT
BB
18
30
None
K
WT
FW
NOTE: 1. Contact factory for availability.
Part Number Example:
MT28C128564W18DFW-705 BBWT
09005aef80b10a55
MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN
1
©2003 Micron Technology, Inc.
‡PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY
MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.
1 page  
ADVANCE
128Mb MULTIBANK BURST FLASH
32Mb/64Mb ASYNC/PAGE CellularRAM COMBO
General Description
The MT28C128532W18/W30D and
MT28C128564W18/W30D combination Flash and Cel-
lularRAM are high-performance, high-density, mem-
ory solutions that can significantly improve system
performance. The Flash architecture features a multi-
partition configuration that supports READ-while-
PROGRAM/ERASE operations with no latency. A 4Mb
partition size enables optimal design flexibility.
Two Flash devices are stacked to achieve the 128Mb
density. Each Flash die has a dedicated CE# and OE#
www.DataSheceot4nUtr.coolm, enabling each Flash to be independently select-
able.
The MT28C128532W18/W30D and
MT28C128564W18/W30D stacked Flash devices
enable soft protection for blocks, as read only, by con-
figuring soft protection registers with dedicated com-
mand sequences. For security purposes, two user-
programmable 64-bit chip protection registers are pro-
vided for each Flash device.
The embedded WORD PROGRAM and BLOCK
ERASE functions are fully automated by an on-chip
write state machine (WSM). An on-chip device status
register can be used to monitor the WSM status and
determine the progress of the PROGRAM/ERASE tasks.
Each Flash device has a read configuration register
(RCR) that defines how the Flash interacts with the mem-
ory bus. For device specifications and additional docu-
mentation concerning Flash and CellularRAM features,
please refer to the MT28F644W18/W30 data sheet at
www.micron.com/flash and the MT45W2MW16PFA and
MT45W4MW16PFA data sheets at http://
www.micron.com/cellularram.
The CellularRAM architecture features high-speed
CMOS, dynamic random-access memories developed
for low-power portable applications The CellularRAM
device is available in either 32Mb or 64Mb densities.
To operate seamlessly on a burst Flash bus, Cellular-
RAM products have incorporated a transparent self-
refresh mechanism. The hidden refresh requires no
additional support from the system memory controller
and has no significant impact on device read/write per-
formance.
The refresh configuration register (CR) is used to con-
trol how refresh is performed on the DRAM array. These
registers are automatically loaded with default settings
during power-up and can be updated any time during
normal operation. Special attention has been focused
on standby current consumption during self-refresh.
CellularRAM products include three system-acces-
sible mechanisms used to minimize standby current.
Partial array refresh (PAR) limits refresh to the portion
of the memory array being used. Temperature com-
pensated refresh (TCR) is used to adjust the refresh
rate according to the ambient temperature. The
refresh rate can be decreased at lower temperatures to
minimize current consumption during standby. Deep
power down (DPD) halts the REFRESH operation alto-
gether and is used when no vital information is stored
in the device. These three refresh mechanisms are
adjusted through the CR.
Please refer to Micron’s Web site www.micron.com/
flash for the latest MT28F644W18/W30 Flash data
sheet and http://www.micron.com/cellularram for the
latest MT45W2MW16PFA and MT45W4MW16PFA Cel-
lularRAM data sheet.
Flash Configurations
Each Flash memory implements a multibank archi-
tecture (16 banks of 4Mb each) to allow concurrent
operations. Any address within a block address range
selects that block for the required READ, PROGRAM, or
ERASE operation.
Each Flash memory features eight 4K-word sectors
(8 x 65,536 bits), designated as parameter blocks, and
the remaining part is organized in main blocks of 32K
words each (524,288 bits). The parameter blocks are
addressed either by the low order addresses (bottom
boot) or by the higher order addresses (top boot).
The two Flash devices can be supplied with any
combination of top or bottom boot (e.g., top/top, bot-
tom/bottom, top/bottom, or bottom/top). Please see
Figures 2 and 3 for more information.
09005aef80b10a55
MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
5 Page 
ADVANCE
128Mb MULTIBANK BURST FLASH
32Mb/64Mb ASYNC/PAGE CellularRAM COMBO
Boot Configurations
The possible configurations for Flash die are shown
in Table 4 below. This table shows the possible config-
urations of the two Flash devices for either top boot or
bottom boot: F_CE1# and F_CE2# indicate to which
Flash die the configuration is referred.
Table 4: Possible Boot Configurations
for Flash Die
www.DataSheeCtO4UN.cFoImGURATION
Top/Top
Bottom/Top
Top/Bottom
Bottom/Bottom
F_CE1#
Top
Bottom
Top
Bottom
F_CE2#
Top
Top
Bottom
Bottom
ORDER
CODE
TT
BT
TB
BB
MultiChip Packaging Considerations
Multichip packaging presents unique chal-
lenges when controlling complex memory devices.
The MT28C128532W18/W30D and
MT28C128564W18/W30D devices combine two
Micron Flash devices with a single CellularRAM
device.
Unique IDs, State Machines, and
Registers
Each Flash device has a separate command state
machine (CSM) and status register (SR) and read con-
figuration register (RCR). The RCR settings are sepa-
rate and can be different for the upper and lower
device. Each Flash device has its own OTP, CFI, and
device code. Depending on the boot configuration of
each Flash device, the OTP, CFI, and device code infor-
mation may differ.
Both Flash devices will share the same ManID,
either Micron (0x2Ch) or Intel (0x89h), which is
defined by the part number. (Se Figure 4 on page 9.)
The CellularRAM has a configuration register (CR)
that defines how the device performs self refresh.
Command Codes
All Flash command codes are independent
within each device. Care must be taken when
crossing the array boundary between the upper
and lower Flash and the CellularRAM to ensure
that only one device is enabled at one time.
In a two-cycle command sequence such as word
program (0x40/data), it is required that both com-
mands be issued to the same device.
It is not recommended that READ and ERASE
operations occur simultaneously on two devices.
READ Operation
Page and burst read modes are limited to the
address boundaries of each device. A new page/ burst
operation must be started when crossing a device
boundary.
Flash Reset
The reset control is shared by both Flash die.
Bringing RST# control LOW will reset both the
upper and lower device.
Power Consumption
Multiple chip packaging requires that power
calculations consider the active operation of the
upper and lower Flash as well as that of the Cellu-
larRAM. Total power consumed will be the sum of
the currents associated with the state of each
device. Table 9 on page 14 shows the power con-
sumption specifications.
09005aef80b10a55
MT28C128564W18D_B.fm - Rev. B, Pub 7/03 EN
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology. Inc.
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet MT28C128564W30D.PDF ] | |
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