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PDF 16V8B Data sheet ( Hoja de datos )
| Número de pieza | 16V8B | |
| Descripción | ATF16V8B | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de 16V8B (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
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Features
• Industry-standard Architecture
– Emulates Many 20-pin PALs®
– Low-cost Easy-to-use Software Tools
• High-speed Electrically-erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-pin Delay
• Several Power Saving Options
Device
ATF16V8B
ICC, Standby
50 mA
ICC, Active
55 mA
ATF16V8BQ
ATF16V8BQL
35 mA
5 mA
40 mA
20 mA
• CMOS and TTL Compatible Inputs and Outputs
– Input and I/O Pull-up Resistors
• Advanced Flash Technology
– Reprogrammable
– 100% Tested
ww•wH.Diagtha-Srheelieat4bUil.ictyomCMOS Process
– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity
• Commercial, and Industrial Temperature Ranges
• Dual-in-line and Surface Mount Packages in Standard Pinouts
• PCI-compliant
Block Diagram
High-
performance
EE PLD
ATF16V8B
ATF16V8BQ
ATF16V8BQL
Pin Configurations
All Pinouts Top View
Pin Name Function
CLK Clock
I Logic Inputs
I/O Bi-directional Buffers
OE Output Enable
VCC
+5V Supply
TSSOP
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I/O
12 I/O
11 I9/OE
DIP/SOIC
PLCC
I/CLK
I1
I2
I3
I4
I5
I6
I7
I8
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 I/O
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
13 I/O
12 I/O
11 I9/OE
I3 4
I4 5
I5 6
I6 7
I7 8
18 I/O
17 I/O
16 I/O
15 I/O
14 I/O
Rev. 0364I–04/01
1
1 page  
Input Test Waveforms and
Measurement Levels:
ATF16V8B(QL)
Output Test Loads:
Commercial
tR, tF < 5 ns (10% to 90%)
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ Max
Units
Conditions
wwwC.DINataSheet4U.com
5
8
pF
VIN = 0 V
COUT
68
pF
VOUT = 0 V
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
Power-up Reset
The registers in the ATF16V8Bs are designed to reset dur-
ing power-up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. As a result,
the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin high,
and
3. The clock must remain stable during tPR.
Preload of Registered Outputs
The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since any state can be
forced into the registers to control test sequencing. A
JEDEC file with preload is generated when a source file
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.
Parameter
tPR
VRST
Description
Power-up
Reset Time
Power-up
Reset Voltage
Typ Max Units
600 1,000
ns
3.8 4.5
V
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATF16V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.
The security fuse should be programmed last, as its effect
is immediate.
5
5 Page 
Simple Mode Logic Diagram
ATF16V8B(QL)
www.DataSheet4U.com
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet 16V8B.PDF ] | |
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