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PDF LPC2148 Data sheet ( Hoja de datos )

Número de pieza LPC2148
Descripción (LPC2141 - LPC2148) Single-chip 16-bit/32-bit microcontrollers
Fabricantes NXP Semiconductors 
Logotipo NXP Semiconductors Logotipo

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1. Datasheet - 16/32 Bit Microcontroller






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LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash
with ISP/IAP, USB 2.0 full-speed device, 10-bit ADC and DAC
Rev. 5 — 12 August 2011
Product data sheet
1. General description
The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S
CPU with real-time emulation and embedded trace support, that combine the
microcontroller with embedded high-speed flash memory ranging from 32 kB to 512 kB. A
128-bit wide memory interface and a unique accelerator architecture enable 32-bit code
execution at the maximum clock rate. For critical code size applications, the alternative
16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty.
Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal for
applications where miniaturization is a key requirement, such as access control and
point-of-sale. Serial communications interfaces ranging from a USB 2.0 Full-speed
device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB up to 40 kB,
make these devices very well suited for communication gateways and protocol
converters, soft modems, voice recognition and low end imaging, providing both large
buffer size and high processing power. Various 32-bit timers, single or dual 10-bit ADC(s),
10-bit DAC, PWM channels and 45 fast GPIO lines with up to nine edge or level sensitive
external interrupt pins make these microcontrollers suitable for industrial control and
medical systems.
2. Features and benefits
2.1 Key features
16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package.
8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory.
128-bit wide interface/accelerator enables high-speed 60 MHz operation.
In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot
loader software. Single flash sector or full chip erase in 400 ms and programming of
256 B in 1 ms.
EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the
on-chip RealMonitor software and high-speed tracing of instruction execution.
USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM.
In addition, the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA.
One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14
analog inputs, with conversion times as low as 2.44 s per channel.
Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only).
Two 32-bit timers/external event counters (with four capture and four compare
channels each), PWM unit (six outputs) and watchdog.
Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input.

1 page




LPC2148 pdf
NXP Semiconductors
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
P0.21/PWM5/CAP1.3 1
P0.22/CAP0.0/MAT0.0 2
RTCX1 3
P1.19/TRACEPKT3 4
RTCX2 5
VSS
VDDA
P1.18/TRACEPKT2
6
7
8
P0.25/AD0.4/AOUT 9
D+ 10
D11
P1.17/TRACEPKT1 12
P0.28/AD0.1/CAP0.2/MAT0.2 13
P0.29/AD0.2/CAP0.3/MAT0.3 14
P0.30/AD0.3/EINT3/CAP0.0 15
P1.16/TRACEPKT0 16
LPC2142
48 P1.20/TRACESYNC
47 P0.17/CAP1.2/SCK1/MAT1.2
46 P0.16/EINT0/MAT0.2/CAP0.2
45 P0.15/EINT2
44 P1.21/PIPESTAT0
43 VDD
42 VSS
41 P0.14/EINT1/SDA1
40 P1.22/PIPESTAT1
39 P0.13/MAT1.1
38 P0.12/MAT1.0
37 P0.11/CAP1.1/SCL1
36 P1.23/PIPESTAT2
35 P0.10/CAP1.0
34 P0.9/RXD1/PWM6/EINT3
33 P0.8/TXD1/PWM4
002aab734
Fig 3. LPC2142 pinning
LPC2141_42_44_46_48
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 12 August 2011
© NXP B.V. 2011. All rights reserved.
5 of 45

5 Page





LPC2148 arduino
NXP Semiconductors
Table 3. Pin description …continued
Symbol
Pin Type
P1.23/
PIPESTAT2
36[6]
I/O
O
P1.24/
TRACECLK
32[6]
I/O
O
P1.25/EXTIN0
28[6]
I/O
P1.26/RTCK
24[6]
I
I/O
I/O
P1.27/TDO
P1.28/TDI
P1.29/TCK
P1.30/TMS
P1.31/TRST
D+
D
RESET
XTAL1
XTAL2
RTCX1
RTCX2
VSS
VSSA
VDD
64[6]
60[6]
56[6]
52[6]
20[6]
10[7]
11[7]
57[8]
I/O
O
I/O
I
I/O
I
I/O
I
I/O
I
I/O
I/O
I
62[9]
I
61[9]
O
3[9][10]
I
5[9][10]
O
6, 18, 25, 42, I
50
59 I
23, 43, 51 I
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
Description
P1.23 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
PIPESTAT2 — Pipeline Status, bit 2.
P1.24 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
TRACECLK — Trace Clock.
P1.25 — General purpose input/output digital pin (GPIO). Standard
I/O port with internal pull-up.
EXTIN0 — External Trigger Input.
P1.26 — General purpose input/output digital pin (GPIO).
RTCK — Returned Test Clock output. Extra signal added to the JTAG
port. Assists debugger synchronization when processor frequency
varies. Bidirectional pin with internal pull-up.
Note: LOW on RTCK while RESET is LOW enables pins P1[31:26] to
operate as Debug port after reset.
P1.27 — General purpose input/output digital pin (GPIO).
TDO — Test Data out for JTAG interface.
P1.28 — General purpose input/output digital pin (GPIO).
TDI — Test Data in for JTAG interface.
P1.29 — General purpose input/output digital pin (GPIO).
TCK — Test Clock for JTAG interface. This clock must be slower than
16 of the CPU clock (CCLK) for the JTAG interface to operate.
P1.30 — General purpose input/output digital pin (GPIO).
TMS — Test Mode Select for JTAG interface.
P1.31 — General purpose input/output digital pin (GPIO).
TRST — Test Reset for JTAG interface.
USB bidirectional D+ line.
USB bidirectional Dline.
External reset input: A LOW on this pin resets the device, causing
I/O ports and peripherals to take on their default states, and processor
execution to begin at address 0. TTL with hysteresis, 5 V tolerant.
Input to the oscillator circuit and internal clock generator circuits.
Output from the oscillator amplifier.
Input to the RTC oscillator circuit.
Output from the RTC oscillator circuit.
Ground: 0 V reference.
Analog ground: 0 V reference. This should nominally be the same
voltage as VSS, but should be isolated to minimize noise and error.
3.3 V power supply: This is the power supply voltage for the core and
I/O ports.
LPC2141_42_44_46_48
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 12 August 2011
© NXP B.V. 2011. All rights reserved.
11 of 45

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