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MD1213 の電気的特性と機能

MD1213のメーカーはSupertexです、この部品の機能は「High Speed Dual MOSFET Driver」です。


製品の詳細 ( Datasheet PDF )

部品番号 MD1213
部品説明 High Speed Dual MOSFET Driver
メーカ Supertex
ロゴ Supertex ロゴ 




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MD1213 Datasheet, MD1213 PDF,ピン配置, 機能
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MD1213
High Speed Dual MOSFET Driver
Features
6ns rise and fall time with 1000pF load
2.0A peak output source/sink current
1.2V to 5V input CMOS compatible
4.5V to 13V total supply voltage
Smart logic threshold
Low jitter design
Two matched channels
Outputs can swing below ground
Low inductance package
Thermally-enhanced package
Applications
Medical ultrasound imaging
Piezoelectric transducer drivers
Nondestructive evaluation
PIN diode driver
CCD Clock driver/buffer
High speed level translator
General Description
The Supertex MD1213 is a high speed, dual MOSFET driver. It is
designed to drive high voltage P and N-channel MOSFET transistors
for medical ultrasound and other applications requiring a high
output current for a capacitive load. The high-speed input stage of
the MD1213 can operate from 1.2V to 5.0V logic interface with an
optimum operating input signal range of 1.8V to 3.3V. An adaptive
threshold circuit is used to set the level translator switch threshold
to the average of the input logic 0 and logic 1 levels. The input logic
levels may be ground referenced, even though the driver is putting out
bipolar signals. The level translator uses a proprietary circuit, which
provides DC coupling together with high-speed operation.
The output stage of the MD1213 has separate power connections
enabling the output signal L and H levels to be chosen independently
from the supply voltages used for the majority of the circuit. As an
example, the input logic levels may be 0 and 1.8volts, the control logic
may be powered by +5.0V and –5.0V, and the output L and H levels
may be varied anywhere over the range of –5.0V to +5.0V. The output
stage is capable of peak currents of up to ±2.0A, depending on the
supply voltages used and load capacitance present.
The OE pin serves a dual purpose. First, its logic H level is used
to compute the threshold voltage level for the channel input level
translators. Secondly, when OE is low, the outputs are disabled, with
the A output high and the B output low. This assists in properly pre-
charging the AC coupling capacitors that may be used in series in the
gate drive circuit of an external PMOS and NMOS transistor pair.
Typical Application Circuit
VDD1
OE Level
Shifter
INA Level
Shifter
VDD2
+5V
VH 0.47µF
OUTA
3.3V CMOS
Logic Inputs
VSS2
VDD2
INB Level
Shifter
MD1213
Gnd VSS1
VSS2
10nF
VL
VH
10nF
OUTB
VL -5V
0.47µF
Supertex
TC6320
+100V
1µF
To Piezoelectric
Transducer
-100V
1µF

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MD1213 pdf, ピン配列
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MD1213
Outputs (VH = VDD1 = VDD2 = 12V, VL = VSS1 = VSS2 = 0V, VOE = 3.3V, TJ = 25°C)
Sym Parameter
Min Typ Max
VIH OE Input logic voltage high
1.2 - 5.0
VIL OE Input logic voltage low
0 - 0.3
RIN Input logic impedance to GND 12 20 30
CIN Logic input capacitance
- 5.0 10
θJA Thermal resistance to air
- 47 -
θJC
RSINK
RSOURCE
ISINK
ISOURCE
Thermal resistance to case
Output sink resistance
Output source resistance
Peak output sink current
Peak output source current
- 7.0 -
- - 12.5
- - 12.5
- 2.0 -
- 2.0 -
Units Conditions
V
V For logic input OE
pF All inputs
°C/W
1oz. 4-layer 3x4” PCB with thermal
pad and thermal via array
°C/W ---
Ω ISINK = 50mA
Ω ISOURCE = 50mA
A ---
A ---
AC Electrical Characteristics (VH = VDD1 = VDD2 = 12V, VL = VSS1 = VSS2 = 0V, VOE = 3.3V, TJ = 25°C)
Sym Parameter
Min Typ Max Units Conditions
tirf Inputs or OE rise & fall time
tPLH
Propagation delay when out-
put is from low to high
- - 10 ns Logic input edge speed requirement
- 7.0 - ns
tPHL
Propagation delay when out-
put is from high to low
tPOE
Propagation delay OE to
outputs
- 7.0 - ns CLOAD = 1000pF,
see timing diagram
- 9.0 - ns Input signal rise/fall time of 2ns
tr
tf
l tr - tf l
l tPLH-tPHL l
Output rise time
Output fall time
Rise and fall time matching
Propagation low to high and
high to low matching
- 6.0 - ns
- 6.0 - ns
- 1.0 - ns
For each channel
- 1.0 - ns
Δtdm Propagation delay match
- ±2.0 -
ns Device to device delay match
Logic Truth Table
OE
H
H
H
H
L
Logic Inputs
INA
L
L
H
H
X
INB
L
H
L
H
X
OUTA
VH
VH
VL
VL
VH
Output
OUTB
VH
VL
VH
VL
VL
3


3Pages


MD1213 電子部品, 半導体
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MD1213
Application Information
For proper operation of the MD1213, low inductance bypass
capacitors should be used on the various supply pins. The
GND input pin should be connected to the digital ground.
The INA, INB, and OE pins should be connected to their
logic source with a swing of GND to logic level high, which is
1.2V to 5.0V. Good trace practices should be followed corre-
sponding to the desired operating speed. The internal circuit-
ry of the MD1213 is capable of operating up to 100MHz, with
the primary speed limitation being the loading effects of the
load capacitance. Because of this speed and the high tran-
sient currents that result with capacitive loads, the bypass
capacitors should be as close to the chip pins as possible.
Unless the load specifically requires bipolar drive, the V ,
SS1
VSS2, and VL pins should have low inductance feed-through
connections directly to a ground plane. If these voltages are
not zero, then they need bypass capacitors in a manner sim-
ilar to the positive power supplies. The power connections
VDD1 and VDD2 should have a ceramic bypass capacitor to the
ground plane with short leads and decoupling components to
prevent resonance in the power leads. A common capacitor
and voltage source may be used for these two pins, which
should always have the same DC voltage applied. For ap-
plications sensitive to jitter and noise, separate decoupling
networks may be used for VDD1 and VDD2.
The supplied voltages of VH and VL determine the output
logic levels. These two pins can draw fast transient currents
of up to 2.0A, so they should be provided with an appropri-
ate bypass capacitor located next to the chip pins. A ceramic
capacitor of up to 1.0µF may be appropriate, with a series
ferrite bead to prevent resonance in the power supply lead
coming to the capacitor. Pay particular attention to minimiz-
ing trace lengths and using sufficient trace width to reduce
inductance. Surface mount components are highly recom-
mended. Since the output impedance of this driver is very
low, in some cases it may be desirable to add a small series
resistor in series with the output signal to obtain better wave-
form integrity at the load terminals.
This will of course reduce the output voltage slew rate at
the terminals of a capacitive load. Pay particular attention
to the parasitic coupling from the driver output to the input
signal terminals. This feedback may cause oscillations or
spurious waveform shapes on the edges of signal transi-
tions. Since the input operates with signals down to 1.2V,
even small coupled voltages may cause problems. Use of a
solid ground plane and good power and signal layout prac-
tices will prevent this problem. Be careful that the circulating
ground return current from a capacitive load cannot react
with common inductance to cause noise voltages in the in-
put logic circuitry.
Pin Description
Pin # Name Description
1
INA
Logic input. Controls OUTA when OE is high. Input logic high will cause the output to swing to VL. Input
logic low will cause the output to swing to VH.
2 V Supply voltage for N-channel output stage.
L
3
INB
Logic input. Controls OUTB when OE is high. Input logic high will cause the output to swing to VL. Input
logic low will cause the output to swing to VH.
4 GND Logic input ground reference.
5 VSS1 Low side analog circuit and level shifter supply voltage. Should be at the same potential as VSS2.
6 V Low side gate drive supply voltage.
SS2
Output driver. Swings from VH to VL. Intended to drive the gate of an external N-channel MOSFET via a
7 OUTB series capacitor. When OE is low, the output is disabled. OUTB will swing to VL turning off the external
N-channel MOSFET.
8 VH Supply voltage for P-channel output stage.
Output driver. Swings from VH to VL. Intended to drive the gate of an external P-channel MOSFET via a
9 OUTA series capacitor. When OE is low, the output is disabled. OUTA will swing to VH turning off the external
P-channel MOSFET.
10 VDD2 High side gate drive supply voltage.
11 VDD1 High side analog circuit and level shifter supply voltage. Should be at the same potential as VDD2.
Output-enable logic input. When OE is high, (VOE + VGND)/2 sets the threshold transition between logic
12 OE level high and low for INA and INB. When OE is low, OUTA is at VH and OUTB is at VL regardless of INA
and INB
Note: 1.Thermal Pad and Pin#5 (VSS1) must be connected externally.
2. Index Pad and Thermal Pad are connected internally
6

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