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DS0056 の電気的特性と機能

DS0056のメーカーはNational Semiconductorです、この部品の機能は「Dual High-Speed MOS Driver」です。


製品の詳細 ( Datasheet PDF )

部品番号 DS0056
部品説明 Dual High-Speed MOS Driver
メーカ National Semiconductor
ロゴ National Semiconductor ロゴ 




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DS0056 Datasheet, DS0056 PDF,ピン配置, 機能
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October 2000
DS0026
Dual High-Speed MOS Driver
General Description
DS0026 is a low cost monolithic high speed two phase MOS
clock driver and interface circuit. Unique circuit design pro-
vides both very high speed operation and the ability to drive
large capacitive loads. The device accepts standard TTL
outputs and converts them to MOS logic levels. The device
may be driven from standard 54/74 series and 54S/74S
series gates and flip-flops or from drivers such as the
DS8830 or DM7440. The DS0026 is intended for applica-
tions in which the output pulse width is logically controlled;
i.e., the output pulse width is equal to the input pulse width.
The DS0026 is designed to fulfill a wide variety of MOS
interface requirements. Information on the correct usage of
the DS0026 in these as well as other systems is included in
the application note AN-76.
Features
n Fast rise and fall times — 20 ns 1000 pF load
n High output swing — 20V
n High output current drive — ±1.5 amps
n TTL compatible inputs
n High rep rate — 5 to 10 MHz depending on power
dissipation
n Low power consumption in MOS “0” state — 2 mW
n Drives to 0.4V of GND for RAM address drive
Connection Diagram (Top View)
Dual-In-Line Package
DS005853-2
Order Number DS0026CN
See NS Package Number N08E
© 2000 National Semiconductor Corporation DS005853
www.national.com

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Typical VBB Connection
Typical Performance Characteristics
DS005853-8
Input Current vs Input Voltage
Supply Current vs Temperature
Turn-On and Turn-Off Delay
vs Temperature
Rise Time vs Load
Capacitance
DS005853-22
DS005853-23
Fall Time vs Load
Capacitance
DS005853-24
DS005853-25
DS005853-26
3 www.national.com


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Application Hints (Continued)
FIGURE 3. Clock Waveform
DS005853-18
Controlling the clock ringing is particularly difficult because of
the relative magnitude of the allowable ringing, compared to
magnitude of the transition. In this case it is 1V out of 20V or
only 5%. Ringing can be controlled by damping the clock
driver and minimizing the line inductance.
Damping the clock driver by placing a resistance in series
with its output is effective, but there is a limit since it also
slows down the rise and fall time of the clock signal. Because
the typical clock driver can be much faster than the worst
case driver, the damping resistor serves the useful function
of limiting the minimum rise and fall time. This is very impor-
tant because the faster the rise and fall times, the worse the
ringing problem becomes. The size of the damping resistor
varies because it is dependent on the details of the actual
application. It must be determined empirically. In practice a
resistance of 10to 20is usually optimum.
Limiting the inductance of the clock lines can be accom-
plished by minimizing their length and by laying out the lines
such that the return current is closely coupled to the clock
lines. When minimizing the length of clock lines it is impor-
tant to minimize the distance from the clock driver output to
the furthest point being driven. Because of this, memory
boards are usually designed with clock drivers in the center
of the memory array, rather than on one side, reducing the
maximum distance by a factor of 2.
Using multilayer printed circuit boards with clock lines sand-
wiched between the VDD and VSS power plains minimizes
the inductance of the clock lines. It also serves the function
of preventing the clocks from coupling noise into input and
output lines. Unfortunately multilayer printed circuit boards
are more expensive than two sided boards. The user must
make the decision as to the necessity of multilayer boards.
Suffice it to say here, that reliable memory boards can be
designed using two sided printed circuit boards.
DS005853-19
FIGURE 4. Clock Waveforms (Voltage and Current)
Because of the amount of current that the clock driver must
supply to its capacitive load, the distribution of power to the
clock driver must be considered. Figure 4 gives the idealized
voltage and current waveforms for a clock driver driving a
1000 pF capacitor with 20 ns rise and fall time.
As can be seen the current is significant. This current flows
in the VDD and VSS power lines. Any significant inductance in
the lines will produce large voltage transients on the power
supplies. A bypass capacitor, as close as possible to the
clock driver, is helpful in minimizing this problem. This by-
pass is most effective when connected between the VSS and
VDD supplies. The size of the bypass capacitor depends on
the amount of capacitance being driven. Using a low induc-
tance capacitor, such as a ceramic or silver mica, is most
effective. Another helpful technique is to run the VDD and
VSS lines, to the clock driver, adjacent to each other. This
tends to reduce the lines inductance and therefore the mag-
nitude of the voltage transients.
While discussing the clock driver, it should be pointed out
that the DS0026 is a relatively low input impedance device.
It is possible to couple current noise into the input without
seeing a significant voltage. Since the noise is difficult to
detect with an oscilloscope it is often overlooked.
Lastly, the clock lines must be considered as noise genera-
tors. Figure 5 shows a clock coupled through a parasitic
coupling capacitor, CC, to eight data input lines being driven
by a 7404. A parasitic lumped line inductance, L, is also
shown. Let us assume, for the sake of argument, that CC is
1 pF and that the rise time of the clock is high enough to
completely isolate the clock transient from the 7404 because
of the inductance, L.
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