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E8870SP PDF Datasheet ( 特性, スペック, ピン接続図 )

部品番号 E8870SP
部品説明 Scalability Port Switch
メーカ Intel Corporation
ロゴ Intel Corporation ロゴ 



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E8870SP Datasheet, E8870SP PDF,ピン配置, 機能
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Intel® E8870SP Scalability Port Switch
(SPS) Datasheet
Product Features
s Scalability Port (SP):
— Six SPs with 3.2 GB/s peak bandwidth
per direction per SP.
— Bi-directional SPs for a total bandwidth
of 38.4 GB/s.
s Integrated Snoop Filter:
— 1 MB 12-way set associative tag array
capable of maintaining state of 200K
cache lines.
— Partitioned into four interleaves, each
interleave can be accessed in parallel.
— Supports up to 266M look-up and
update (LUU) operations per second.
— Pseudo Least Recently Used (PLRU)
replacement algorithm, with updates on
look-ups and invalidates.
— ECC coverage, with correction of
single bit errors, detection of double bit
errors.
— Fast array initialization and/or self test
through configuration register access.
s Multiple Processor Node Support:
— Conflict detection logic to maintain
memory consistency for coherent
memory across multiple processor
nodes.
— Advanced address mapping and decode
capabilities enable flexible routing of
transactions based on address and/or
transaction type.
s Internal Interconnect:
— A six-ported dual lane crossbar network
routes transaction packets from one SP
port to another.
— Separate bypass buses for low latency
snoop look-up and response connection
between ports and interleaves.
s System Management Bus (SMBus) 2.0
slave interface for server management with
packet error checking.
s Reliability, Availability, and Serviceability
(RAS):
— Sideband access to configuration
registers via SMBus or JTAG.
— End-to-end ECC for all interfaces.
— Fault detection and logging.
— Signal connectivity testing via
boundary scan.
s Packaging:
— 42.5 mm x 42.5 mm.
— 1012-pin organic LAN grid array
(OLGA) package-2B.
Document Number: 252034-001
November 2002

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Scalability Port Switch

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