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PDF E8870SP Data sheet ( Hoja de datos )
| Número de pieza | E8870SP | |
| Descripción | Scalability Port Switch | |
| Fabricantes | Intel Corporation | |
| Logotipo |  |
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Intel® E8870SP Scalability Port Switch
(SPS) Datasheet
Product Features
s Scalability Port (SP):
— Six SPs with 3.2 GB/s peak bandwidth
per direction per SP.
— Bi-directional SPs for a total bandwidth
of 38.4 GB/s.
s Integrated Snoop Filter:
— 1 MB 12-way set associative tag array
capable of maintaining state of 200K
cache lines.
— Partitioned into four interleaves, each
interleave can be accessed in parallel.
— Supports up to 266M look-up and
update (LUU) operations per second.
— Pseudo Least Recently Used (PLRU)
replacement algorithm, with updates on
look-ups and invalidates.
— ECC coverage, with correction of
single bit errors, detection of double bit
errors.
— Fast array initialization and/or self test
through configuration register access.
s Multiple Processor Node Support:
— Conflict detection logic to maintain
memory consistency for coherent
memory across multiple processor
nodes.
— Advanced address mapping and decode
capabilities enable flexible routing of
transactions based on address and/or
transaction type.
s Internal Interconnect:
— A six-ported dual lane crossbar network
routes transaction packets from one SP
port to another.
— Separate bypass buses for low latency
snoop look-up and response connection
between ports and interleaves.
s System Management Bus (SMBus) 2.0
slave interface for server management with
packet error checking.
s Reliability, Availability, and Serviceability
(RAS):
— Sideband access to configuration
registers via SMBus or JTAG.
— End-to-end ECC for all interfaces.
— Fault detection and logging.
— Signal connectivity testing via
boundary scan.
s Packaging:
— 42.5 mm x 42.5 mm.
— 1012-pin organic LAN grid array
(OLGA) package-2B.
Document Number: 252034-001
November 2002
1 page  
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6.2.1
6.2.2
6.2.3
6.2.4
Spread Spectrum Support.....................................................................6-1
No Stop Clock or Thermal Shutdown ....................................................6-1
SMBus Clocking ....................................................................................6-1
JTAG Test Access Port .........................................................................6-1
7 Reliability, Availability and Serviceability.........................................................................7-1
7.1 Data Integrity ......................................................................................................7-1
7.1.1 End-to-End Error Detection ...................................................................7-1
7.1.2 Error Reporting......................................................................................7-2
7.1.3 Interface Details ....................................................................................7-3
7.1.4 Time-out ................................................................................................7-3
8 Electrical Specification ....................................................................................................8-1
8.1 Non-operational Maximum Rating......................................................................8-1
8.2 Operational Power Delivery Specification ..........................................................8-1
8.3 Scalability Port Signal Group..............................................................................8-2
8.4 SMBus and TAP Electrical Specifications ..........................................................8-2
8.5 DC Specifications ...............................................................................................8-3
8.6 AC Specifications ...............................................................................................8-4
8.6.1 AC Timing Waveforms ..........................................................................8-5
8.7 Miscellaneous Signal Pins..................................................................................8-6
8.7.1 Signal Groups........................................................................................8-6
8.7.2 DC Characteristics ................................................................................8-7
8.8 AC Specification .................................................................................................8-8
8.9 Intel® E8870 Chipset Clock Signal Groups ........................................................8-9
9 Ballout and Package Information ....................................................................................9-1
9.1 1012-Ball OLGA2b Package Information ...........................................................9-1
10 Testability ......................................................................................................................10-1
10.1 Test Access Port ..............................................................................................10-1
10.1.1 The TAP Logic.....................................................................................10-1
10.1.2 Accessing the TAP Logic ....................................................................10-2
10.2 Public TAP Instructions ....................................................................................10-4
10.3 TAP Registers ..................................................................................................10-5
Figures
1-1
4-1
4-2
8-1
8-2
8-3
9-1
9-2
9-3
10-1
10-2
10-3
10-4
SPS Block Diagram............................................................................................1-2
System Memory Address Space ........................................................................4-1
Example of Mapping MMIO Regions..................................................................4-3
TAP DC Thresholds ...........................................................................................8-4
TAP and SMBus Valid Delay Timing Waveform ................................................8-5
TCK and SM_CLK Clock Waveform ..................................................................8-6
1012-Ball OLGA2b Package Dimensions – Top View .......................................9-1
1012-Ball OLGA2b Package Dimensions – Bottom View ..................................9-2
1012-Ball OLGA2b Solder Ball Detail.................................................................9-3
TAP Controller Signals .....................................................................................10-1
Simplified Block Diagram of TAP Controller.....................................................10-2
TAP Controller State Diagram..........................................................................10-3
TAP Instruction Register ..................................................................................10-6
Intel® E8870SP Scalability Port Switch (SPS) Datasheet
v
5 Page 
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Signal Descriptions
2
2.1 Conventions
The terms assertion and deassertion are used extensively when describing signals, to avoid
confusion when working with a mix of active-high and active-low signals. The term assert, or
assertion, indicates that the signal is active, independent of whether the active level is represented
by a high or low voltage. The term deassert, or deassertion, indicates that the signal is inactive.
Signal names may or may not have a “#” appended to them. The “#” symbol at the end of a signal
name indicates that the active, or asserted state occurs when the signal is at a low voltage level.
When “#” is not present after the signal name the signal is asserted when at the high voltage level.
When discussing data values used inside the component, the logical value is used. For instance.,a
data value described as “1101b” would appear as “1101b” on an active-high bus, and as “0010b”
on an active-low bus. When discussing the assertion of a value on the actual signal, the physical
value is used; i.e. asserting an active-low signal produces a “0” value on the signal.
Table 2-1 and Table 2-2 list the reference terminology used later for buffer technology types (e.g.
SBD, etc.) and buffering signal types (e.g. input, output, etc.).
Table 2-1. Buffer Technology Types
Buffer Type
SBD
Differential
SPCMOS
CMOS OD
SMBus OD
JTAG
Analog
Description
Simultaneous bi-directional.
A differential input that requires a voltage reference or
the signal compliment.
CMOS type I/O with Schmidt trigger input.
CMOS open drain I/O.
SMBus open drain I/O with Schmidt trigger input with a
voltage level of 3.3V and max. frequency of 100 KHz.
1.5V JTAG I/O.
Typically a voltage reference or specialty power supply.
Table 2-2. Buffer Signal Directions
Buffer Direction
Description
I Input pin.
O Output pin.
I/O Bi-directional (input/output) pin.
Some signals or groups of signals have multiple versions. These signal groups may represent
distinct, but similar, ports or interfaces or they may represent identical copies of the signal used to
reduce loading effects. Table 2-3 shows the conventions the SPS uses.
Intel® E8870SP Scalability Port Switch (SPS) Datasheet
2-1
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