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D72103A の電気的特性と機能

D72103AのメーカーはNECです、この部品の機能は「 UPD72103A」です。


製品の詳細 ( Datasheet PDF )

部品番号 D72103A
部品説明 UPD72103A
メーカ NEC
ロゴ NEC ロゴ 




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D72103A Datasheet, D72103A PDF,ピン配置, 機能
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µPD72103A
HDLC CONTROLLER
© 1997
µPD72103A
Document No. S10766EJ9V0UM00 (9th edition)
Date Published March 1997 N CP(N)
Printed in Japan

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D72103A pdf, ピン配列
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V25+ is a trademark of NEC Corporation.
The export of this product from Japan is prohibited without governmental license. To export or re-export this product from
a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
The information in this document is subject to change without notice.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property
rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M7 96.5


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D72103A 電子部品, 半導体
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TABLE OF CONTENTS
CHAPTER 1 GENERAL ............................................................................................................................ 1
1.1 Features ..................................................................................................................................... 1
1.2 Block Diagram .......................................................................................................................... 2
1.3 Internal Block Functions ......................................................................................................... 3
1.4 Pin Configuration (Top View) ................................................................................................. 4
1.5 Pin Functions ........................................................................................................................... 6
1.6 Initialization via Reset ........................................................................................................... 11
CHAPTER 2 BUS INTERFACE ..............................................................................................................13
2.1 Internal Registers ...................................................................................................................13
2.1.1 Control register ............................................................................................................................. 14
2.1.2 Internal status register .................................................................................................................. 15
2.2 DMAC (Direct Memory Access Controller) .........................................................................16
2.2.1 Block transfers .............................................................................................................................. 16
2.2.2 Extension of active (low-level) width of MRD and MWR signals ................................................... 17
2.2.3 Basic timing of DMA ...................................................................................................................... 18
2.2.4 Address/data multiplexing ............................................................................................................. 20
2.3 Interface between µPD72103A and Host Processor ......................................................... 22
2.3.1 Command issuance ...................................................................................................................... 23
2.3.2 Status report ................................................................................................................................. 25
2.3.3 Command chain function .............................................................................................................. 26
2.4 Initialization of External Memory .........................................................................................27
2.5 Methods for Using External Memory .................................................................................. 27
2.5.1 Command table ............................................................................................................................. 27
2.5.2 Status table ................................................................................................................................... 32
2.5.3 Receive buffer address table ........................................................................................................ 36
2.5.4 Receive buffer ............................................................................................................................... 45
2.5.5 Transmit buffer .............................................................................................................................. 45
2.5.6 External memory table configuration example .............................................................................. 45
CHAPTER 3 COMMUNICATION OPERATIONS ...................................................................................47
3.1 Initial Settings ........................................................................................................................47
3.2 Start of Communication Control Operation and Flag Synchronization Setup ............. 48
3.2.1 Transmit operation ........................................................................................................................ 48
3.2.2 Receive operation ......................................................................................................................... 48
3.2.3 Status reporting ............................................................................................................................. 48
3.3 Data Transmission .................................................................................................................49
3.3.1 Transmission timing ...................................................................................................................... 49
3.3.2 Linkage of transmit data ................................................................................................................ 49
3.3.3 Transmit buffer chain .................................................................................................................... 50
3.3.4 Transmission underrun ................................................................................................................. 50
3.4 Data Reception .......................................................................................................................51
3.4.1 Reception timing ........................................................................................................................... 51
3.4.2 Separation of receive data ............................................................................................................ 53
–i–

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部品番号部品説明メーカ
D72103A

UPD72103A

NEC
NEC


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