48LC8M8A2 Datasheet PDF - Micron Technology
| Part Number | 48LC8M8A2 | |
| Description | MT48LC8M8A2 | |
| Manufacturers | Micron Technology | |
| Logo |  |
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SYNCHRONOUS
DRAM
FEATURES
• PC66-, PC100-, and PC133-compliant
• Fully synchronous; all signals registered on
positive edge of system clock
• Internal pipelined operation; column address can
be changed every clock cycle
• Internal banks for hiding row access/precharge
• Programmable burst lengths: 1, 2, 4, 8, or full page
• Auto Precharge, includes CONCURRENT AUTO
PRECHARGE, and Auto Refresh Modes
• Self Refresh Modes: standard and low power
• 64ms, 4,096-cycle refresh
• LVTTL-compatible inputs and outputs
• Single +3.3V ±0.3V power supply
OPTIONS
MARKING
• Configurations
16 Meg x 4 (4 Meg x 4 x 4 banks)
16M4
8 Meg x 8 (2 Meg x 8 x 4 banks)
8M8
4 Meg x 16 (1 Meg x 16 x 4 banks)
4M16
• WRITE Recovery (tWR)
tWR = “2 CLK”1
A2
• Plastic Package – OCPL2
54-pin TSOP II (400 mil)
TG
• Timing (Cycle Time)
10ns @ CL = 2 (PC100)
7.5ns @ CL = 3 (PC133)
7.5ns @ CL = 2 (PC133)
6ns @ CL = 3 (PC133, x16 Only)
-8E 3, 4,5
-75
-7E
-6
• Self Refresh
Standard
Low Power
None
L
• Operating Temperature Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
None
IT 3
Part Number Example:
MT48LC8M8A2TG-75
NOTE: 1. Refer to Micron Technical Note: TN-48-05.
2. Off-center parting line.
3. Consult Micron for availability.
4. Not recommended for new designs.
5. Shown for PC100 compatibility.
64Mb: x4, x8, x16
SDRAM
MT48LC16M4A2 – 4 Meg x 4 x 4 banks
MT48LC8M8A2 – 2 Meg x 8 x 4 banks
MT48LC4M16A2 – 1 Meg x 16 x 4 banks
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/dramds
PIN ASSIGNMENT (Top View)
x4 x8 x16
- - VDD
NC DQ0 DQ0
- - VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
- - VssQ
NC NC DQ3
NC DQ2 DQ4
- - VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
- - VssQ
NC NC DQ7
- - VDD
NC NC DQML
- - WE#
- - CAS#
- - RAS#
- - CS#
- - BA0
- - BA1
- - A10
- - A0
- - A1
- - A2
- - A3
- - VDD
54-Pin TSOP
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9 46
10 45
11 44
12 43
13 42
14 41
15 40
16 39
17 38
18 37
19 36
20 35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
x16 x8 x4
Vss - -
DQ15 DQ7 NC
VssQ - -
DQ14 NC NC
DQ13 DQ6 DQ3
VDDQ -
-
DQ12 NC NC
DQ11 DQ5 NC
VssQ - -
DQ10 NC NC
DQ9 DQ4 DQ2
VDDQ -
-
DQ8 NC NC
Vss - -
NC - -
DQMH DQM DQM
CLK - -
CKE - -
NC - -
A11 - -
A9 - -
A8 - -
A7 - -
A6 - -
A5 - -
A4 - -
Vss - -
Note: The # symbol indicates signal is active LOW. A dash (–)
indicates x8 and x4 pin function is same as x16 pin function.
Configuration
Refresh Count
Row Addressing
Bank Addressing
Column Addressing
16 Meg x 4
4 Meg x 4 x 4 banks
4K
4K (A0-A11)
4 (BA0, BA1)
1K (A0-A9)
8 Meg x 8
2 Meg x 8 x 4 banks
4K
4K (A0-A11)
4 (BA0, BA1)
512 (A0-A8)
4 Meg x 16
1 Meg x 16 x 4 banks
4K
4K (A0-A11)
4 (BA0, BA1)
256 (A0-A7)
KEY TIMING PARAMETERS
SPEED
GRADE
-6
-7E
-75
-7E
-8E 3, 4, 5
-75
-8E 3, 4, 5
CLOCK
FREQUENCY
166 MHz
143 MHz
133 MHz
133 MHz
125 MHz
100 MHz
100 MHz
ACCESS TIME SETUP
CL = 2* CL = 3* TIME
– 5.5ns 1.5ns
– 5.4ns 1.5ns
– 5.4ns 1.5ns
5.4ns – 1.5ns
– 6ns 2ns
6ns – 1.5ns
6ns – 2ns
HOLD
TIME
1ns
0.8ns
0.8ns
0.8ns
1ns
0.8ns
1ns
* CL = CAS (READ) latency
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
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FUNCTIONAL BLOCK DIAGRAM
8 Meg x 8 SDRAM
64Mb: x4, x8, x16
SDRAM
CKE
CLK
CS#
WE#
CAS#
RAS#
CONTROL
LOGIC
BANK3
BANK2
BANK1
MODE REGISTER
12
A0-A11,
BA0, BA1
14
ADDRESS
REGISTER
REFRESH 12
COUNTER
12
ROW-
ADDRESS
MUX
12
BANK0
ROW-
ADDRESS
LATCH
&
DECODER
4096
BANK0
MEMORY
ARRAY
(4,096 x 512 x 8)
SENSE AMPLIFIERS
4096
2
BANK
CONTROL
LOGIC
2
COLUMN-
ADDRESS
9
9 COUNTER/
LATCH
I/O GATING
DQM MASK LOGIC
READ DATA LATCH
WRITE DRIVERS
512
(x8)
COLUMN
DECODER
11
DATA
8 OUTPUT
REGISTER
DATA
8 INPUT
REGISTER
8
DQM
DQ0-DQ7
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
5 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003, Micron Technology, Inc.
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