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STEL-2060C の電気的特性と機能

STEL-2060CのメーカーはIntelです、この部品の機能は「45Mbps Viterbi Decoder」です。


製品の詳細 ( Datasheet PDF )

部品番号 STEL-2060C
部品説明 45Mbps Viterbi Decoder
メーカ Intel
ロゴ Intel ロゴ 




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STEL-2060C Datasheet, STEL-2060C PDF,ピン配置, 機能
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STEL-2060C/CR
Data Sheet
STEL-2060C/CR
45 Mbps
Viterbi Decoder
R

1 Page





STEL-2060C pdf, ピン配列
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PIN CONFIGURATION
Package: 100-pin HQFP
Thermal coefficient, θja = 30° C/W
0.941"
± 0.010"
0.742"
±0.005"
80
81
51
50
Top View
0.11" nom.
Pin 1 Identifier
100
1
0.0256" ±0.002"
0.014"
± 0.002"
0.487" 0.705"
±0.003" ± 0.010"
31
30
0.122" max.
0.009"
± 0.005"
0.031"
± 0.005"
Detail of pins
Notes:
(1) Tolerances on pin spacing are not cumulative
(2) Dimensions shown are at seating plane
(3) I.C. denotes Internal Connection. This pin must be left unconnected. Do not use for vias.
(4) N.C. denotes No Connection. These pins can be used for vias.
PIN CONNECTIONS
1 VDD
2 N.C.
3 N.C.
4 G10
5 G11
6 G12
7 G20
8 G21
9 G22
10 N.C.
11 OBIN
12 N.C.
13 VSS
14 SYMCKIN
15 N.C.
16 VSS
17 DCLKIN
18 N.C.
19 VSS
20 RESET
21 VSS
22 N.C.
23 PNCG1
24 PNCG2
25 DSCRAM
26 SYNC
27 LDG2
28 N.C.
29 N.C.
30 VDD
31 VDD
32 COUNT0
33 COUNT1
34 COUNT2
35 COUNT3
36 COUNT4
37 COUNT5
38 COUNT6
39 COUNT7
40 VDD
41 VSS
42 VDD
43 PARL
44 READ
45 VSS
46 ADDR2
47 ADDR1
48 ADDR0
49 WRITE
50 CSEL
51 VDD
52 VDD
53 N.C.
54 DATA7
55 DATA6
56 DATA5
57 DATA4
58 DATA3
59 DATA2
60 DATA1
61 DATA0
62 N.C.
63 INT
64 N.C.
65 VSS
66 ODCLK
67 N.C.
68 VSS
69 DATO
70 N.C.
71 OOS
72 AUTO
73 N.C.
74 I.C.
75 N.C.
76 BERR
77 G1ERR
78 G2ERR
79 VDD
80 VDD
81 THR0
82 THR1
83 THR2
84 THR3
85 THR4
86 THR5
87 THR6
88 THR7
89 EXTSEL
90 VSS
91 VSS
92 VSS
93 VDD
94 VSS
95 DDIF
96 VSS
97 RATE2
98 RATE1
99 RATE0
100 VDD
3 STEL-2060C


3Pages


STEL-2060C 電子部品, 半導体
www.DataSheet4U.com
ADDR2-0
The 3-bit address bus is used to access the various I/O
functions, as shown in the Memory Map table, below. Note
that some addresses contain both Read and Write registers.
These read and write mode registers are separate and contain
different data.
WRITE
The Write input is used to write data to the microprocessor
data bus. It is active low and is normally connected to the
write line of the host processor.
READ
The Read input is used to read data from the microprocessor
data bus. It is active low and is normally connected to the
read line of the host processor.
CSEL
The Chip Select input can be used to selectively enable the
microprocessor data bus. It is active low.
INT
The Interrupt output indicates when the Period Counter in
the BER Monitor has completed a count period, and that a
new value of BERCT is ready to be read from addresses 0H
and 1H, when INT will go high for one symbol period.
INPUT (WRITE) FUNCTIONS
COUNT7-0
The 8-bit COUNT7-0 data defines the period (i.e., the number
of bits) used in the node synchronization circuit. The 8-bit
number N is used to set up a period of (256N + 256) internally,
where N is the value of COUNT7-0. If the renormalization
count exceeds the threshold value during a period of this
number of bits then an out-of-sync condition is declared (i.e.,
the output pin OOS is set high and AUTO pulses high).
Reset value 00H.
THR7-0
The 8-bit THR7-0 data defines the threshold for node
synchronization when EXTSEL is set low. The function is
identical to that of the THR7-0 input signal. Reset value 00H.
BPER23-0
The 24-bit BER Period data is used to set the period (number
of data bits) over which the mean BER is measured by the
BER Monitor. The period used is 1000 times the value of
BPER23-0. Reset value FFFFFFH.
Note: The BER Count function incorporated in the
STEL-2060CCC uses a counter to count the number of
thousands of bits received. When the value of this counter is
equal to the value written into BPER23-0 the number of errors
counted is dumped into the BERCT15-0 output register and
can be read from read addresses 0-1H. Simultaneously, both
the error and bit counters are reset and the process is restarted,
and an interrupt (INT) is generated to indicate that the new
value is ready to be read.
Since the default (reset) value of the BPER23-0 register is
FF FF FFH a potential problem occurs if the desired value is
not written into this register before the value of the counter
has already incremented past this value. If this is not done
the equality will not be detected until after the counter
overflows and increments to the desired value once again.
Even at the maximum rate of 45 Mbps this will take over 6
minutes and, at a more modest data rate, such as 1 Mbps, it
will take over 41/2 hours! In any case, the user can easily be
misled into believing that the circuit is not operating correctly
since the interrupts will not be generated as expected. It is
therefore imperative that the BPER23-0 value be written into
the STEL-2060CCC as soon as possible after a reset to ensure
that this condition does not take place. The maximum time
allowable is just less than the desired interrupt period itself,
since the counter begins counting right after the reset is
released.
e.g., if the desired interrupt period is one second, the
BPER23-0 value must be written within one second of the
reset. At a data rate of 1 Mbps the period would correspond
to 106 bits and the correct BPER23-0 value would be 103, or
00 03 E8H.
If, for some reason, it is not possible to do this, a dummy
value should first be written into the STEL-2060CCC. This
should be large enough so that, at the time of writing, the bit
counter will not have exceeded the dummy value. In this
way the first interrupt will be generated within a reasonable
period of time and the dummy value can then be overwritten
with the desired value. Again, care must be taken to ensure
that the BPER23-0 value written is greater than the
instantaneous counter value, otherwise the same problem
will occur.
e.g., in the above example, if it is not possible to write the
BPER23-0 value until 5 seconds after the reset, then a dummy
BPER23-0 value corresponding to >5 seconds, e.g., 6 seconds,
or 00 17 70H should first be written. The desired value of
00 03 E8H must then be written within one second of an
interrupt generated by the STEL-2060CCC, thereby ensuring
that the counter has not exceeded the new value at that time.
OUTPUT (READ) FUNCTIONS
BERCT15-0
The 16-bit Bit Error Count data represents the mean Bit Error
Rate over the period determined by the BER Period data
BPER23-0. The actual BER is given by:
BER =
8 x BERCT15-0
1000 x BPER23-0
The value will be updated each time the period counter
completes its count. Completion is indicated by the INT
output going high for one clock cycle. If the accumulator
overflows during a measurement period its output will be
caused to saturate at a value of FFFFH.
STEL-2060C
6

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共有リンク

Link :


部品番号部品説明メーカ
STEL-2060

45Mbps Viterbi Decoder

Stanford Telecommunications
Stanford Telecommunications
STEL-2060C

45Mbps Viterbi Decoder

Intel
Intel
STEL-2060CR

45Mbps Viterbi Decoder

Intel
Intel


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