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CY7C1471V33 の電気的特性と機能

CY7C1471V33のメーカーはCypress Semiconductorです、この部品の機能は「(CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY7C1471V33
部品説明 (CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY7C1471V33 Datasheet, CY7C1471V33 PDF,ピン配置, 機能
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CY7C1471V33
CY7C1473V33
CY7C1475V33
72-Mbit (2M x 36/4M x 18/1M x 72)
Flow-Through SRAM with NoBL™ Architecture
Features
Functional Description [1]
• No Bus Latency™ (NoBL™) architecture eliminates dead
cycles between write and read cycles
• Supports up to 133 MHz bus operations with zero wait states
• Data is transferred on every clock
• Pin compatible and functionally equivalent to ZBT™ devices
• Internally self timed output buffer control to eliminate the
need to use OE
• Registered inputs for flow through operation
• Byte Write capability
• 3.3V/2.5V IO supply (VDDQ)
• Fast clock-to-output times
— 6.5 ns (for 133-MHz device)
• Clock Enable (CEN) pin to enable clock and suspend
operation
• Synchronous self timed writes
• Asynchronous Output Enable (OE)
• CY7C1471V33, CY7C1473V33 available in
JEDEC-standard Pb-free 100-Pin TQFP, Pb-free and
non-Pb-free 165-Ball FBGA package. CY7C1475V33
available in Pb-free and non-Pb-free 209-Ball FBGA
package
• Three Chip Enables (CE1, CE2, CE3) for simple depth
expansion
• Automatic power down feature available using ZZ mode or
CE deselect
• IEEE 1149.1 JTAG Boundary Scan compatible
• Burst Capability — linear or interleaved burst order
• Low standby power
The CY7C1471V33, CY7C1473V33 and CY7C1475V33 are
3.3V, 2M x 36/4M x 18/1M x 72 synchronous flow through burst
SRAMs designed specifically to support unlimited true
back-to-back read or write operations without the insertion of
wait states. The CY7C1471V33, CY7C1473V33 and
CY7C1475V33 are equipped with the advanced No Bus
Latency (NoBL) logic required to enable consecutive read or
write operations with data being transferred on every clock
cycle. This feature dramatically improves the throughput of
data through the SRAM, especially in systems that require
frequent write-read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. The clock input is qualified by
the Clock Enable (CEN) signal, which when deasserted
suspends operation and extends the previous clock
cycle.Maximum access delay from the clock rise is 6.5 ns
(133-MHz device).
Write operations are controlled by two or four Byte Write Select
(BWX) and a Write Enable (WE) input. All writes are conducted
with on-chip synchronous self timed write circuitry.
Three synchronous Chip Enables (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. To avoid bus contention,
the output drivers are synchronously tri-stated during the data
portion of a write sequence.
Selection Guide
Maximum Access Time
Maximum Operating Current
Maximum CMOS Standby Current
133 MHz
6.5
305
120
117 MHz
8.5
275
120
Unit
ns
mA
mA
Note
1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines.
Cypress Semiconductor Corporation
Document #: 38-05288 Rev. *J
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised July 04, 2007

1 Page





CY7C1471V33 pdf, ピン配列
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CY7C1471V33
CY7C1473V33
CY7C1475V33
Logic Block Diagram – CY7C1475V33 (1M x 72)
A0, A1, A
MODE
CLK C
CEN
ADDRESS
REGISTER 0
WRITE ADDRESS
REGISTER 1
A1 D1
Q1 A1'
A0 D0 BURST Q0 A0'
ADV/LD
LOGIC
C
WRITE ADDRESS
REGISTER 2
ADV/LD
BW a
BW b
BW c
BW d
BW e
BW f
BW g
BW h
WE
OE
CE1
CE2
CE3
ZZ
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
Sleep Control
WRITE
DRIVERS
MEMORY
ARRAY
S
E
N
S
E
A
M
P
S
O
U
T
P
U
T
R
E
G
I
S
T
E
R
S
E
O
U
T
DP
AU
TT
A
B
SU
TF
EF
EE
RR
IS
N
G
E
INPUT
REGISTER
1
E
INPUT
REGISTER
0
E
DQ s
DQ Pa
DQ Pb
DQ Pc
DQ Pd
DQ Pe
DQ Pf
DQ Pg
DQ Ph
Document #: 38-05288 Rev. *J
Page 3 of 32


3Pages


CY7C1471V33 電子部品, 半導体
www.DataSheet4U.com
CY7C1471V33
CY7C1473V33
CY7C1475V33
Pin Configurations (continued)
12
A NC/576M A
B NC/1G
A
C DQPC NC
D
DQC
DQC
E
DQC
DQC
F
DQC
DQC
G
DQC
DQC
H NC NC
J
DQD
DQD
K
DQD
DQD
L
DQD
DQD
M
DQD
DQD
N DQPD NC
P NC/144M A
R MODE
A
12
A NC/576M A
B NC/1G
A
C NC NC
D NC DQB
E NC DQB
F NC DQB
G NC DQB
H NC NC
J DQB NC
K DQB NC
L DQB NC
M DQB NC
N DQPB NC
P NC/144M A
R MODE
A
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout
CY7C1471V33 (2M x 36)
3
CE1
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
4
BWC
BWD
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
BWB
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
A0
7
CEN
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
ADV/LD
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
A
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
3
CE1
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
CY7C1473V33 (4M x 18)
4
BWB
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
5
NC
BWA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
6
CE3
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1
A0
7
CEN
WE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
ADV/LD
OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
A
A
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
10
A
A
NC
DQB
DQB
DQB
DQB
NC
DQA
DQA
DQA
DQA
NC
A
A
11
NC
NC
DQPB
DQB
DQB
DQB
DQB
ZZ
DQA
DQA
DQA
DQA
DQPA
NC/288M
A
10
A
A
NC
NC
NC
NC
NC
NC
DQA
DQA
DQA
DQA
NC
A
A
11
A
NC
DQPA
DQA
DQA
DQA
DQA
ZZ
NC
NC
NC
NC
NC
NC/288M
A
Document #: 38-05288 Rev. *J
Page 6 of 32

6 Page



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部品番号部品説明メーカ
CY7C1471V33

(CY7C147xV33) 72-Mbit (2M x 36/4M x 18/1M x 72) Flow-Through SRAM

Cypress Semiconductor
Cypress Semiconductor


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