DataSheet.jp

72V221L15PFG の電気的特性と機能

72V221L15PFGのメーカーはIDTです、この部品の機能は「IDT72V221L15PFG」です。


製品の詳細 ( Datasheet PDF )

部品番号 72V221L15PFG
部品説明 IDT72V221L15PFG
メーカ IDT
ロゴ IDT ロゴ 




このページの下部にプレビューと72V221L15PFGダウンロード(pdfファイル)リンクがあります。

Total 14 pages

No Preview Available !

72V221L15PFG Datasheet, 72V221L15PFG PDF,ピン配置, 機能
www.DataSheet4U.com
3.3 VOLT CMOS SyncFIFO™
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9 and 8,192 x 9
IDT72V201, IDT72V211
IDT72V221, IDT72V231
IDT72V241, IDT72V251
FEATURES:
256 x 9-bit organization IDT72V201
512 x 9-bit organization IDT72V211
1,024 x 9-bit organization IDT72V221
2,048 x 9-bit organization IDT72V231
4,096 x 9-bit organization IDT72V241
8,192 x 9-bit organization IDT72V251
10 ns read/write cycle time
5V input tolerant
Read and Write clocks can be independent
Dual-Ported zero fall-through time architecture
Empty and Full Flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags can be set to
any depth
Programmable Almost-Empty and Almost-Full flags default to
Empty+7, and Full-7, respectively
Output Enable puts output data bus in high-impedance state
Advanced submicron CMOS technology
Available in 32-pin plastic leaded chip carrier (PLCC) and 32-pin
plastic Thin Quad FlatPack (TQFP)
Industrial temperature range (–40°C to +85°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72V201/72V211/72V221/72V231/72V241/72V251 SyncFIFOs™
FUNCTIONAL BLOCK DIAGRAM
are very high-speed, low-power First-In, First-Out (FIFO) memories with
clocked read and write controls. The architecture, functional operation and pin
assignments are identical to those of the IDT72201/72211/72221/72231/
72241/72251, but operate at a power supply voltage (Vcc) between 3.0V and
3.6V. These devices have a 256, 512, 1,024, 2,048, 4,096 and 8,192 x 9-bit
memory array, respectively. These FIFOs are applicable for a wide variety of
data buffering needs such as graphics, local area networks and interprocessor
communication.
These FIFOs have 9-bit input and output ports. The input port is
controlled by a free-running clock (WCLK), and two Write Enable pins
(WEN1, WEN2). Data is written into the Synchronous FIFO on every rising
clock edge when the Write Enable pins are asserted. The output port is
controlled by another clock pin (RCLK) and two Read Enable pins (REN1,
REN2). The Read Clock can be tied to the Write Clock for single clock
operation or the two clocks can run asynchronous of one another for dual-
clock operation. An Output Enable pin (OE) is provided on the read port
for three-state control of the output.
The Synchronous FIFOs have two fixed flags, Empty (EF) and Full (FF).
Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are
provided for improved system control. The programmable flags default to
Empty+7 and Full-7 for PAE and PAF, respectively. The programmable flag
offset loading is controlled by a simple state machine and is initiated by asserting
the Load pin (LD).
These FIFOs are fabricated using IDT's high-speed submicron CMOS
technology.
WCLK
WEN1
WEN2
D0 - D8
LD
INPUT REGISTER
OFFSET REGISTER
WRITE CONTROL
LOGIC
WRITE POINTER
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
FLAG
LOGIC
READ POINTER
EF
PAE
PAF
FF
READ CONTROL
LOGIC
OUTPUT REGISTER
RESET LOGIC
RS
OE
Q0 - Q8
RCLK
REN1
REN2
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
©2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
4092 drw 01
FEBRUARY 2006
DSC-4092/4

1 Page





72V221L15PFG pdf, ピン配列
wwwI2D.5DT6a7tx2aVS9,2h50e11e2/t74x2UV9.c2,o11m1,0/7224Vx2291, /27,20V4823x1/97,24V,029461/x729Va2n5d1
3.3V CMOS
8,192 x 9
SyncFIFO™
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ABSOLUTE MAXIMUM RATINGS(1)
RECOMMENDED OPERATING
Symbol
Rating
Com'l & Ind'l Unit CONDITIONS
VTERM(2) Terminal Voltage with
–0.5 to +5
V Symbol
Parameter
Min. Typ. Max. Unit
Respect to GND
VCC Supply Voltage
3.0 3.3 3.6 V
TSTG Storage Temperature
–55 to +125
°C
Commercial/Industrial
IOUT DC Output Current
–50 to +50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VCC terminal only.
GND
VIH
VIL
TA
Supply Voltage
Input High Voltage
Commercial/Industrial
Input Low Voltage
Commercial/Industrial
Operating Temperature
Commercial
0 00V
2.0 — 5.5 V
-0.5 — 0.8 V
0 — 70 °C
TA
Operating Temperature
-40 — 85 °C
Industrial
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C;Industrial: VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
Symbol
Parameter
IDT72V201
IDT72V211
IDT72V221
IDT72V231
IDT72V241
IDT72V251
Commercial and Industrial(1)
tCLK = 10, 15, 20 ns
Min. Typ.
ILI(2) Input Leakage Current (Any Input)
–1 —
ILO(3) OutputLeakageCurrent
–10 —
Max.
1
10
Unit
µA
µA
VOH Output Logic “1” Voltage, IOH = –2mA
2.4 —
—V
VOL
ICC1(4,5,6)
ICC2(4,7)
Output Logic “0” Voltage, IOL = 8mA
Active Power Supply Current
Standby Current
— — 0.4 V
——
20 mA
——
5 mA
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 VIN VCC.
3. OE VIH, 0.4 VOUT VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 0.17 + 0.48*fS + 0.02*CL*fS (in mA) with VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, f = 1.0MHz)
Symbol
Parameter
Conditions
CIN(2) InputCapacitance
VIN = 0V
COUT(1,2) OutputCapacitance
VOUT = 0V
NOTES:
1. With output deselected (OE VIH).
2. Characterized values, not currently tested.
Max.
10
10
Unit
pF
pF
3
FEBRUARY 8, 2006


3Pages


72V221L15PFG 電子部品, 半導体
wwwI2D.5DT6a7tx2aVS9,2h50e11e2/t74x2UV9.c2,o11m1,0/7224Vx2291, /27,20V4823x1/97,24V,029461/x729Va2n5d1
3.3V CMOS
8,192 x 9
SyncFIFO™
IDT72V201 - 256 x 9-BIT
IDT72V211 - 512 x 9-BIT
87
08 7
Empty Offset (LSB) Reg.
Empty Offset (LSB)
Default Value 007H
Default Value 007H
08
8
08
1 08
(MSB)
0
87
Full Offset (LSB) Reg.
Default Value 007H
08 7
Full Offset (LSB)
Default Value 007H
08
8
08
1 08
(MSB)
0
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
IDT72V221 - 1,024 x 9-BIT
7
Empty Offset (LSB) Reg.
Default Value 007H
0
10
(MSB)
00
7
Full Offset (LSB) Reg.
Default Value 007H
0
10
(MSB)
00
IDT72V231 - 2,049 x 9-BIT
IDT72V241 - 4,096 x 9-BIT
IDT72V251 - 8,192 x 9-BIT
87
08
7
08
7
0
Empty Offset (LSB) Reg.
Empty Offset (LSB)
Empty Offset (LSB)
Default Value 007H
Default Value 007H
Default Value 007H
8
2 08
3 08 4 0
(MSB)
(MSB)
(MSB)
000
0000
00000
87
Full Offset (LSB) Reg.
Default Value 007H
08
7
Full Offset (LSB)
Default Value 007H
08
7
Full Offset (LSB)
Default Value 007H
0
8
2 08
3 08 4 0
(MSB)
(MSB)
(MSB)
000
0000
00000
4092 drw 05
Figure 3. Offset Register Location and Default Values
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
6TEMPERATURE RANGES
FEBRUARY 8, 2006

6 Page



ページ 合計 : 14 ページ
 
PDF
ダウンロード
[ 72V221L15PFG データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
72V221L15PFG

IDT72V221L15PFG

IDT
IDT


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap