PDF UC62LV0256 Data sheet ( Hoja de datos )

Número de pieza	UC62LV0256
Descripción	Low Power CMOS SRAM 32K X8 Bits
Fabricantes	ETC
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No Preview Available ! www.DataSheet4U.com Low Power CMOS SRAM 32K X8 Bits UC62LV0256 -35/-55/-70 Features: • Vcc operation voltage : 2.0V ~ 3.6V • Low power consumption : 10mA (Max.) operating current 0.1uA (Typ.) CMOS standby current • High Speed Access time : 35ns (Max.) at Vcc = 2.7V 55ns (Max.) at Vcc = 2.7V 70ns (Max.) at Vcc = 2.0V • Automatic power down when chip is deselected • Three state outputs and TTL compatible • Data retention supply voltage as low as 1.2V • Easy expansion with CE\ and OE\ options PRODUCT FAMILY Product Family Operating Temperature Vcc Range UC62LV0256BC UC62LV0256CC UC62LV0256DC UC62LV0256EC UC62LV0256AC UC62LV0256BI UC62LV0256CI UC62LV0256DI UC62LV0256EI UC62LV0256AI 0 ~ 70 ~ 85 2.0V ~ 3.6V 2.0V ~ 3.6V Speed (ns) Vcc=2.7V -35/ -55/ -70 -35/ -55/ -70 Description The UC62LV0256 is a high performance, very low power CMOS Static Random Access Memory organized as 32,768 words by 8 bits and operates from a wide range of 2.0V to 3.6V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with a typical CMOS standby current of 1uA and maximum access time of 70ns in 2.0V operation. Easy memory expansion is provided enable (CE), and active LOW output enable (OE) and three-state output drivers. The UC62LV0256 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The UC62LV0256 is available in the JEDEC standard 28 pin 330mil Plastic SOP, 300mil Plastic SOJ, 600mil Plastic DIP and 8mmx13.4mm TSOP (normal type). Power Consumption STANDBY VCC=3.6V Operating (Max) Vcc=3.0V 35ns 55ns 70ns 0.1uA 17mA 13mA 10mA 0.1uA 17mA 13mA 10mA Package Type SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE SOP-28 TSOP-28 PDIP-28 SOJ-28 DICE PIN CONFIGURATIONS A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 GND 1 28 2 27 3 UC62LV0256BI 26 4 UC62LV0256DI 25 5 UC62LV0256EI 24 6 UC62LV0256BC 23 UC62LV0256DC 7 UC62LV0256EC 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 VCC WE A13 A8 A9 A11 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 OE A11 A9 A8 A13 WE VCC A14 A12 A7 A6 A5 A4 A3 1 2 3 4 5 6 7 8 9 10 11 12 13 14 UC62LV0256CC UC62LV0256CI 28 A10 27 CE 26 DQ7 25 DQ6 24 DQ5 23 DQ4 22 DQ3 21 GND 20 DQ2 19 DQ1 18 DQ0 17 A0 16 A1 15 A2 BLOCK DIAGRAM CE WE OE ROW Address COL Address CE WE OE MEMORY ARRAY 32K X 8 Bits COLUMN DECODER SENSE AMPLIFIER & WRITE DRIVER X8 I/O BUFFER U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Revision 2.0 PAGE 1 1 page www.DataSheet4U.com Low Power CMOS SRAM 32K X8 Bits SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE1 (1,2,4) ADDRESS DOUT tRC tOH tAA UC62LV0256 -35/-55/-70 tOH READ CYCLE2 (1,3,4) CE DOUT READ CYCLE3 (1,4) tCLZ(5) ADDRESS OE CE DOUT tOLZ tCLZ(5) tCE tRC tAA tOE tCE tCHZ(5) tOH tOHZ(1,5) tCHZ(5) NOTES: 1. WE\ is high in read cycle. 2. Device is continuously selected when CE\ = VIL 3. Address valid prior to or coincident with CE\ transition low. 4. OE\ = VIL. 5. Transition is measured ±500mV from steady state with CL=5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. U-Chip Technology Corp. LTD. Reserves the right to modify document contents without notice. Revision 2.0 PAGE 5 5 Page

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