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U6820BM の電気的特性と機能

U6820BMのメーカーはATMEL Corporationです、この部品の機能は「Dual Quad BCDMOS Driver IC」です。


製品の詳細 ( Datasheet PDF )

部品番号 U6820BM
部品説明 Dual Quad BCDMOS Driver IC
メーカ ATMEL Corporation
ロゴ ATMEL Corporation ロゴ 




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U6820BM Datasheet, U6820BM PDF,ピン配置, 機能
www.DataSheet4U.com
Features
Four Short-circuit-protected High-side Drivers with a Maximum Current Capability of
50 mA Each
Four Short-circuit-protected Low-side Drivers with a Maximum Current Capability of
50 mA Each
ON Resistance High Side Ron < 10 Versus Total Temperature Range
ON Resistance Low Side Ron < 7 Versus Total Temperature Range
Short-circuit Detection of Each Driver Stage
Disabling of Driver Stages in the Case of Short-circuit and Overtemperature Detection
Independent Control of Each Driver Stage via an 8-bit Shift Register
Status Output Reports Short-circuit Condition
Status Output Reports when All Loads Are Switched Off
Timing of Status Output Reset Signalizes Failure Mode
Temperature Protection in Conjunction with Short-circuit Detection
Description
The U6820BM is a driver interface in BCDMOS technology with 8 independent driver
stages having a maximum current capability of 50 mA each. Its partitioning into 4
high-side and 4 low-side driver stages allows an easy connection of either 4 half-
bridges or 2 H-bridges on the pc board. The U6820BM communicates with a micro-
controller via an 8-bit serial interface. Integrated protection against short circuit and
overtemperature give added value. EMI protection and 2-kV ESD protection together
with automotive qualification referring to conducted interference (ISO/TR 7637/1)
make this IC ideal for both automotive and industrial applications.
Figure 1. Block Diagram
VCC
6
HS4 HS3 HS2 HS1
16 9 8 1
Dual Quad
BCDMOS
Driver IC
U6820BM
14
STATUS
CS 11
CLK 12
DI 13
V CC
Current
limiter
Current
limiter
HHHH L L L L
SSSSSSSS
43 2143 21
Input Register
Control
logic
V CC
Current
limiter
Current
limiter
Current
limiter
Current
limiter
3
VS
Thermal protection
V CC
Power-on reset
Current
limiter
Current
limiter
V CC
5 GND S
4
GNDCC
15
LS4
10
LS3
72
LS2 LS1
Rev. 4527ABCD03/02
1

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U6820BM pdf, ピン配列
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U6820BM
Description of the
Control Interface to
the Microcontroller
The serial-parallel interface basically includes an 8-bit shift register (SR), an 8-bit com-
mand register (CR) and a 4-bit counter.
The data input takes place with commands at Pins DI (data input), CS (chip select) and
CLK (clock). With a falling edge at CLK, the information at DI is transferred into the SR.
The first information written into the SR is the least significant bit (LSB). The Pin STA-
TUS is used for diagnostic purposes and reports any fault condition to the
microcontroller.
The input CS in accordance with the CR controls the serial interface. A high level at CS
disables the SR. With a falling edge at CS, the SR is enabled. The CR control allows
only the first 8 bits to be transferred into the SR, and further clocks at CLK are ineffec-
tive. If a rising edge occurs at CS after 8 clocks precisely, the information from the SR is
transferred into the CR. If the number of clock cycles during the low phase of CS was
less or more than eight transitions, no transfer will take place. A new command switches
the output stages on or off immediately.
Each output stage is controlled by one specific bit of the CR. Low level means supply
offor inactive, and high level means supply onor active. If all 8 bits are at a low level,
the output stages will be set into standby mode.
If one of the output stages detects a short circuit and additionally overtemperature con-
dition, the corresponding control bit in the CR is set to low. This reset has priority over
an external command to CR, thus, this does not affect the 1st control bit. The priority pro-
tects the IC against overtemperature by activating the temperature shut down
immediately.
The STATUS Output
The STATUS output is at low level during normal operation. If one or more output stages
detect short circuit or if overtemperature is indicated, the STATUS output changes to
high level (OR-connection).
For diagnostic purposes (self test of the status output), the status output can also be
brought into high level during standby mode.
Timing of the Status
Output Reset Signalizes
the Failure Mode
The use of different reset conditions at the STATUS output simplifies the failure analysis
during normal operation, and is also beneficial during testing.
The storage content can be used for STATUS output. It is indicated and latched immedi-
ately with the rising edge of CS at STATUS output if less than 8 clocks were received
during the low phase of CS. The reset is initiated by the falling edge of the 8th clock
(bit 7) of the next data input.
Also, the appearance of more than 8 clocks is latched and indicated at STATUS by the
rising edge of the 9th clock. The reset is initiated by the falling edge of the 2nd clock
(bit 1) of the next data input.
The detection of overtemperature is latched internally. It is reset by the falling edge of
the 4th clock (bit 3) of a data transfer if overtemperature is no longer present.
Power-on Reset
After switching on the supply voltage, all data latches are reset and the outputs are
switched off. The typical power-on reset threshold is VCC = 3.7 V. The outputs are acti-
vated after the first data transfer.
4527ABCD03/02
3


3Pages


U6820BM 電子部品, 半導体
www.DataSheet4U.com
Figure 4. Block Diagram of the Control Interface
Serial-Parallel Interface
CS
11
8CLK
EN
1
CL
R
Q0
24
Counter
Q1 Q2
8
Q3
CLK
h if 2
h if 4
h if 8
DFF
D
RQ
CL NQ
DFF
D
CL Q
R NQ
POR norm=0
CLK
EN
H4 H3 H2 H1 L4 L3 L2 L1
12 CL
Shift register SR
13 DIN
LSB
DI Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Load CR
DIN DIN DIN DIN DIN DIN DIN DIN
CL Command register BR
NR NQ NR NQ NR NQ NR NQ NR NQ NR NQ NR NQ NR NQ
P-ON-Reset
Th-protection
All norm = 0
DFF
D
RQ
CL NQ
DFF
DQ
R
CL NQ
DFF
DQ
CL
R
NQ
14
STATUS
norm = 0
6 U6820BM
4527ABCD03/02

6 Page



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部品番号部品説明メーカ
U6820BM

Dual Quad BCDMOS Driver IC

ATMEL Corporation
ATMEL Corporation


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