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PDF 74HC3G06 Data sheet ( 特性 )

部品番号 74HC3G06
部品説明 Triple inverter
メーカ NXP Semiconductors
ロゴ NXP Semiconductors ロゴ 

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74HC3G06 Datasheet, 74HC3G06 PDF,ピン配置, 機能
74HC3G06; 74HCT3G06
Triple inverter with open-drain outputs
Rev. 03 — 11 May 2009
Product data sheet
1. General description
The 74HC3G06 and 74HCT3G06 are high-speed Si-gate CMOS devices. They provide
three inverting buffers with open-drain outputs.
The outputs of the 74HC3G06 and 74HCT3G06 devices are open drains and can be
connected to other open-drain outputs to implement active-LOW wired-OR or active-HIGH
wired-AND functions. For digital operation this device must have a pull-up resistor to
establish a logic HIGH-level.
The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.
The HCT device has TTL input switching levels and supply voltage range 4.5 V to 5.5 V.
2. Features
I Wide supply voltage range from 2.0 V to 6.0 V
I High noise immunity
I Low power dissipation
I Multiple package options
I ESD protection:
N HBM JESD22-A114E exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
I Specified from 40 °C to +85 °C and 40 °C to +125 °C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74HC3G06DP
40 °C to +125 °C TSSOP8
74HCT3G06DP
74HC3G06DC
40 °C to +125 °C VSSOP8
74HCT3G06DC
74HC3G06GD
40 °C to +125 °C XSON8U
74HCT3G06GD
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; UTLP based; body 3 × 2 × 0.5 mm

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74HC3G06 pdf, ピン配列
NXP Semiconductors
74HC3G06; 74HCT3G06
Triple inverter with open-drain outputs
6.2 Pin description
Table 3. Pin description
Symbol
Pin
1A, 2A, 3A
1, 3, 6
GND
4
1Y, 2Y, 3Y
7, 5, 2
VCC
8
Description
data input
ground (0 V)
data output
supply voltage
7. Functional description
Table 4. Function table[1]
Input nA
L
H
Output nY
Z
L
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
8. Limiting values
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Max Unit
VCC supply voltage
IIK input clamping current
IOK output clamping current
VO output voltage
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V
active mode
high-impedance mode
0.5
[1] -
[1] 20
[1] 0.5
[1] 0.5
7.0
±20
-
VCC + 0.5
7.0
V
mA
mA
V
V
IO
ICC
IGND
Tstg
PD
output current
supply current
ground current
storage temperature
dynamic power dissipation
VO = 0.5 V to 7.0 V
Tamb = 40 °C to +125 °C
[1] -
[1] -
[1] 50
65
[2] -
25
50
-
+150
300
mA
mA
mA
°C
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8U package: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
74HC_HCT3G06_3
Product data sheet
Rev. 03 — 11 May 2009
© NXP B.V. 2009. All rights reserved.
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3Pages


74HC3G06 電子部品, 半導体
NXP Semiconductors
74HC3G06; 74HCT3G06
Triple inverter with open-drain outputs
Table 8. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); all typical values are measured at Tamb = 25 °C; for test circuit see Figure 7.
Symbol Parameter
Conditions
40 °C to +85 °C
40 °C to +125 °C Unit
Min Typ Max Min
Max
74HCT3G06
tPZL OFF-state to LOW nA to nY; see Figure 6
propagation delay
VCC = 4.5 V
tPLZ LOW to OFF-state nA to nY; see Figure 6
propagation delay
VCC = 4.5 V
tTHL HIGH to LOW output VCC = 4.5 V; see Figure 6
transition time
- 9 24 -
- 12 27 -
- 6 19 -
29 ns
32 ns
22 ns
CPD
power dissipation
VI = GND to VCC 1.5 V [1]
-
capacitance
4
- - pF
[1] CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
12. Waveforms
VI
nA input
GND
VCC
nY output
VOL
VM
tPLZ
VX
Measurement points are given in Table 9.
VOL is the typical output voltage level that occurs with the output load.
Fig 6. The input (nA) to output (nY) propagation delays
tPZL
VM
tTHL
001aak031
Table 9. Measurement points
Type
Input
74HC3G06
74HCT3G06
VM
0.5 × VCC
1.3 V
Output
VM
0.5 × VCC
1.3 V
VX
0.1 × VCC
0.1 × VCC
74HC_HCT3G06_3
Product data sheet
Rev. 03 — 11 May 2009
© NXP B.V. 2009. All rights reserved.
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