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IS62LV12816ALL の電気的特性と機能

IS62LV12816ALLのメーカーはISSIです、この部品の機能は「128K X 16 CMOS Static RAM」です。


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部品番号 IS62LV12816ALL
部品説明 128K X 16 CMOS Static RAM
メーカ ISSI
ロゴ ISSI ロゴ 




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IS62LV12816ALL Datasheet, IS62LV12816ALL PDF,ピン配置, 機能
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IS62LV12816ALL
128K x 16 CMOS STATIC RAM
ISSI ®
MARCH 2001
FEATURES
• High-speed access time: 55, 70, 100 ns
• CMOS low power operation
– 120 mW (typical) operating
– 6 µW (typical) CMOS standby
• TTL compatible interface levels
• Single 2.5V (min.) to 3.45V (max.) power supply
• Fully static operation: no clock or refresh
required
• Three state outputs
• Data control for upper and lower bytes
• Industrial temperature available
• Available in the 44-pin TSOP (Type II) and
48-pin mini BGA (6mm x 8mm)
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
The ISSI IS62LV12816ALL is a high-speed, 2,097,152-bit
static RAM organized as 131,072 words by 16 bits. It is
fabricated using ISSI's high-performance CMOS
technology. This highly reliable process coupled with
innovative circuit design techniques, yields high-performance
and low power consumption devices.
When CE is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down with CMOS input levels.
Easy memory expansion is provided by using Chip Enable
and Output Enable inputs, CE and OE. The active LOW
Write Enable (WE) controls both writing and reading of the
memory. A data byte allows Upper Byte (UB) and Lower
Byte (LB) access.
The IS62LV12816ALL is packaged in the JEDEC standard
44-pin TSOP (Type II) and 48-pin mini BGA. (6mm x 8mm)
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
UB
LB
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
04/17/01
1

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IS62LV12816ALL pdf, ピン配列
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IS62LV12816ALL
ISSI ®
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
40°C to +85°C
VCC MIN.
2.5V
2.5V
VCC MAX.
3.45V
3.45V
1
ABSOLUTE MAXIMUM RATINGS(1)
Symbol
Parameter
Value
Unit
VTERM
Terminal Voltage with Respect to GND
0.5 to Vcc+0.5
V
TBIAS
Temperature Under Bias
40 to +85
°C
VCC Vcc Related to GND
0.3 to +3.6
V
TSTG
Storage Temperature
65 to +150
°C
PT Power Dissipation
1.0 W
Note:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
2
3
4
5
DC ELECTRICAL CHARACTERISTICS (Over Operating Range)
Symbol Parameter
Test Conditions
VOH Output HIGH Voltage
VCC = Min., IOH = 1 mA
VOL Output LOW Voltage
VCC = Min., IOL = 2.1 mA
VIH Input HIGH Voltage
VIL(1)
Input LOW Voltage
ILI Input Leakage
GND VIN VCC
ILO Output Leakage
GND VOUT VCC, Outputs Disabled
Notes:
1. VIL (min.) = 2.0V for pulse width less than 10 ns.
6
7Min.
Max.
Unit
2.0
V
0.4 V
82.2 VCC + 0.2 V
0.2 0.4
V
1 1 µA
91 1 µA
10
CAPACITANCE(1)
Symbol Parameter
Conditions
Max.
Unit
CIN Input Capacitance
VIN = 0V
6 pF
COUT
Input/Output Capacitance
VOUT = 0V
8 pF
Note:
1. Tested initially and after any design or process changes that may affect these parameters.
11
12
Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. A
04/17/01
3


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IS62LV12816ALL 電子部品, 半導体
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IS62LV12816ALL
AC WAVEFORMS
READ CYCLE NO. 2(1,3) (CS, OE, AND UB/LB Controlled)
ADDRESS
OE
tRC
tAA
CE
LB, UB
DOUT
tLZCE
tLZB
HIGH-Z
tDOE
tLZOE
tACE
tBA
DATA VALID
tOHA
tHZOE
tHZCE
tHZB
Notes:
1. WE is HIGH for a Read Cycle.
2. The device is continuously selected. OE, CE, UB, or LB = VIL.
3. Address is valid prior to or coincident with CE LOW transition.
ISSI ®
WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)
Symbol Parameter
-55
Min. Max.
-70
Min. Max.
-100
Min. Max.
Unit
tWC Write Cycle Time
55
70
100
ns
tSCE CE to Write End
50
65
80
ns
tAW Address Setup Time to Write End 50
65
80
ns
tHA Address Hold from Write End
0
0
0
ns
tSA Address Setup Time
0
0
0
ns
tPWB
LB, UB Valid to End of Write
45
60
80
ns
tPWE
WE Pulse Width
45
60
80
ns
tSD Data Setup to Write End
25
30
40
ns
tHD Data Hold from Write End
0
0
0
ns
tHZWE(3) WE LOW to High-Z Output
30
30
40
ns
tLZWE(3) WE HIGH to Low-Z Output
5
5
5
ns
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to
2.2V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CE LOW and UB or LB, and WE LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to
the rising or falling edge of the signal that terminates the write.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
6 Integrated Silicon Solution, Inc. 1-800-379-4774
Rev. A
04/17/01

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部品番号部品説明メーカ
IS62LV12816ALL

128K X 16 CMOS Static RAM

ISSI
ISSI


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