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PDF IS62LV12816L Data sheet ( Hoja de datos )
| Número de pieza | IS62LV12816L | |
| Descripción | ULTRA LOW POWER CMOS STATIC RAM | |
| Fabricantes | Integrated Circuit Solution | |
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IS62LV12816Lwww.DISat6aS2hLeVet14U2.8co1m6L
IISS626LV21L28V161L2L 816LL
128K x 16 LOW VOLTAGE, ULTRA
LOW POWER CMOS STATIC RAM
FEATURES
High-speed access times: 55, 70, 100 ns
CMOS low power operation
-- 120 mW (typical) operating
-- 6 µW (typical) CMOS standby
TTL compatible interface levels
Single 2.7V-3.6V Vcc power supply
Fully static operation: no clock or refresh re-
quired
Three state outputs
Data control for upper and lower bytes
Industrial temperature available
Available in the 44-pin TSOP-2 and 48-pin
6*8mm TF-BGA
DESCRIPTION
The 1+51 IS62LV12816L and IS62LV12816LL are high-speed,
2.097,152-bit static RAMs organized as 131,072 words by 16
bits. They are fabricated using 1+51's high-performance CMOS
technology. This highly reliable process coupled with innova-
tive circuit design techniques, yields high-performance and
low power consumption devices.
When CE is HIGH (deselected) or when CE is low and both LB
and UB are HIGH, the device assumes a standby mode at
which the power dissipation can be reduced by using CMOS
input levels.
Easy memory expansion is provided by using Chip Enable
Output and Enable inputs, CE and OE. The active LOW Write
Enable (WE) controls both writing and reading of the memory.
A data byte allows Upper Byte (UB) and Lower Byte (LB)
access.
The IS62LV12816L and IS62LV12816LL are packaged in the
JEDEC standare 44-pin 400mil TSOP-2 and 48-pin 6*8mm
TF-BGA.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K x 16
MEMORY ARRAY
VCC
GND
I/O0-I/O7
Lower Byte
I/O8-I/O15
Upper Byte
I/O
DATA
CIRCUIT
COLUMN I/O
CE
OE CONTROL
WE CIRCUIT
UB
LB
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
Integrated Circuit Solution Inc.
SR020-0C
1
1 page  
www.DISat6aS2hLeVet14U2.8co1m6L
IS62LV12816LL
IS62LV12816LL POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
ICC Vcc Dynamic Operating
Supply Current
ISB TTL Standby Current
(TTL Inputs)
OR
Test Conditions
VCC = Max.,
IOUT = 0 mA, f = fMAX
VCC = Max.,
VIN = VIH or VIL,
CE ≥ VIH, f = 0
-55
Min. Max.
Com. 40
Ind. 45
Com. 0.4
Ind. 1.0
-70
Min. Max.
30
35
0.4
1.0
-100
Min. Max.
20
25
0.4
1.0
Unit
mA
mA
ULB Control
VCC = Max., VIN = VIH or VIL
CE = VIL, f = 0, UB = VIH, LB = VIH
ISB CMOS Standby
VCC = Max., f = 0
Com. 10
Current (CMOS Inputs) CE ≥ VCC 0.2V,
Ind. 15
VIN ≥ VCC 0.2V, or
VIN ≤ 0.2V, f = 0
OR
10
15
10
15
µA
ULB Control
VCC = Max., CE = VIL
VIN ≤ 0.2V, f = 0, UB / LB = VCC 0.2V
Note:
1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter
tRC Read Cycle Time
tAA Address Access Time
tOHA Output Hold Time
tACE CE Access Time
tDOE OE Access Time
tHZOE OE to High-Z Output
tLZOE OE to Low-Z Output
tHZCE CE to High-Z Output
tLZCE CE to Low-Z Output
tBA LB, UB Access Time
tHZB LB, UB o High-Z Output
tLZB LB. UB to Low-Z Output
-55
Min. Max.
55
55
10
55
30
20
5
0 20
10
55
0 25
0
-70
Min. Max.
70
70
10
70
35
25
5
0 25
10
70
0 25
0
-100
Min. Max.
100
100
15
100
50
30
5
0 30
10
100
0 35
0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.3V, input pulse levels
of 0.4V to 2.2V and output loading specified in Figure 1.
2. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
Integrated Circuit Solution Inc.
SR020-0C
5
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