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EP2C5Q208C8N の電気的特性と機能

EP2C5Q208C8NのメーカーはAlteraです、この部品の機能は「Cyclon II Device」です。


製品の詳細 ( Datasheet PDF )

部品番号 EP2C5Q208C8N
部品説明 Cyclon II Device
メーカ Altera
ロゴ Altera ロゴ 




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EP2C5Q208C8N Datasheet, EP2C5Q208C8N PDF,ピン配置, 機能
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Cyclone II Device Handbook, Volume 1
101 Innovation Drive
San Jose, CA 95134
(408) 544-7000
http://www.altera.com
CII5V1-3.1

1 Page





EP2C5Q208C8N pdf, ピン配列
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Contents
Chapter Revision Dates ........................................................................... xi
About This Handbook ............................................................................ xiii
How to Contact Altera .......................................................................................................................... xiii
Typographic Conventions .................................................................................................................... xiii
Section I. Cyclone II Device Family Data Sheet
Revision History .................................................................................................................................... 1–1
Chapter 1. Introduction
Introduction ............................................................................................................................................ 1–1
Low-Cost Embedded Processing Solutions .................................................................................. 1–1
Low-Cost DSP Solutions ................................................................................................................. 1–1
Features ................................................................................................................................................... 1–2
Document Revision History ................................................................................................................. 1–8
Chapter 2. Cyclone II Architecture
Functional Description .......................................................................................................................... 2–1
Logic Elements ....................................................................................................................................... 2–2
LE Operating Modes ........................................................................................................................ 2–4
Logic Array Blocks ................................................................................................................................ 2–7
LAB Interconnects ............................................................................................................................ 2–8
LAB Control Signals ......................................................................................................................... 2–8
MultiTrack Interconnect ..................................................................................................................... 2–10
Row Interconnects .......................................................................................................................... 2–10
Column Interconnects .................................................................................................................... 2–12
Device Routing ............................................................................................................................... 2–15
Global Clock Network & Phase-Locked Loops ............................................................................... 2–16
Dedicated Clock Pins ..................................................................................................................... 2–20
Dual-Purpose Clock Pins .............................................................................................................. 2–20
Global Clock Network ................................................................................................................... 2–21
Global Clock Network Distribution ............................................................................................ 2–23
PLLs .................................................................................................................................................. 2–25
Embedded Memory ............................................................................................................................. 2–27
Memory Modes ............................................................................................................................... 2–30
Clock Modes .................................................................................................................................... 2–31
M4K Routing Interface .................................................................................................................. 2–31
Embedded Multipliers ........................................................................................................................ 2–32
Altera Corporation
iii


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EP2C5Q208C8N 電子部品, 半導体
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VCCA & GNDA ............................................................................................................................. 7–30
VCCD & GND ................................................................................................................................. 7–33
Conclusion ............................................................................................................................................ 7–33
Section III. Memory
Revision History .................................................................................................................................... 7–1
Chapter 8. Cyclone II Memory Blocks
Introduction ............................................................................................................................................ 8–1
Overview ................................................................................................................................................. 8–1
Control Signals .................................................................................................................................. 8–3
Parity Bit Support ............................................................................................................................. 8–4
Byte Enable Support ........................................................................................................................ 8–4
Packed Mode Support ..................................................................................................................... 8–6
Address Clock Enable ...................................................................................................................... 8–6
Memory Modes ...................................................................................................................................... 8–8
Single-Port Mode .............................................................................................................................. 8–9
Simple Dual-Port Mode ................................................................................................................. 8–10
True Dual-Port Mode ..................................................................................................................... 8–12
Shift Register Mode ........................................................................................................................ 8–14
ROM Mode ...................................................................................................................................... 8–16
FIFO Buffer Mode ........................................................................................................................... 8–16
Clock Modes ......................................................................................................................................... 8–16
Independent Clock Mode .............................................................................................................. 8–17
Input/Output Clock Mode ........................................................................................................... 8–19
Read/Write Clock Mode ............................................................................................................... 8–22
Single-Clock Mode ......................................................................................................................... 8–24
Power-Up Conditions & Memory Initialization ........................................................................ 8–27
Read-During- Write Operation at the Same Address .................................................................... 8–28
Same-Port Read-During-Write Mode .......................................................................................... 8–28
Mixed-Port Read-During-Write Mode ........................................................................................ 8–29
Conclusion ............................................................................................................................................ 8–30
Chapter 9. External Memory Interfaces
Introduction ............................................................................................................................................ 9–1
External Memory Interface Standards ................................................................................................ 9–2
DDR & DDR2 SDRAM .................................................................................................................... 9–2
QDRII SRAM ..................................................................................................................................... 9–5
Cyclone II DDR Memory Support Overview .................................................................................... 9–9
Data & Data Strobe Pins ................................................................................................................ 9–10
Clock, Command & Address Pins ............................................................................................... 9–14
Parity, DM & ECC Pins ................................................................................................................. 9–14
Phase Lock Loop (PLL) .................................................................................................................. 9–15
Clock Delay Control ....................................................................................................................... 9–15
DQS Postamble ............................................................................................................................... 9–16
vi
Cyclone II Device Handbook, Volume 1
Altera Corporation

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共有リンク

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部品番号部品説明メーカ
EP2C5Q208C8

Cyclon II Device

Altera
Altera
EP2C5Q208C8N

Cyclon II Device

Altera
Altera


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