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PDF GS1545 Data sheet ( Hoja de datos )
| Número de pieza | GS1545 | |
| Descripción | HDTV Serial Digital Equalizing Receiver | |
| Fabricantes | Gennum Corporation | |
| Logotipo |  |
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FEATURES
• SMPTE 292M compliant
• 1.485 and 1.485/1.001Gb/s operation
• integrated adaptive cable equalizer
• integrated adjustment-free reclocker
• 1:20 serial to parallel conversion
• selectable reclocked serial output
• analog/digital input MUX
• carrier detect
• LOCK detect
• input jitter indicator (IJI)
• cable length indication
• maximum cable length adjust
• 20 bit output
• 74.25MHz or 74.25/1.001MHz clock output
• single +5.0V power supply
• minimal component count for HD SDI receive
solutions
APPLICATIONS
SMPTE 292M Serial Digital Interfaces for Video Cameras,
Camcorders, VTR's, Signal Generators, Portable
Equipment, and NLE's.
HD-LINX™ GS1545
HDTV Serial Digital
Equalizing Receiver
PRELIMINARY DATA SHEET
DESCRIPTION
The GS1545 is a high performance integrated Equalizing
Receiver designed for HDTV component signals,
conforming to the SMPTE 292M standard. The GS1545
includes adjustment free, adaptive cable equalization, clock
and data recovery, and serial to parallel conversion.
The Equalizer stage features DC restoration for immunity to
the DC content in pathological test patterns.
The Clock and Data Recovery stage was designed to
automatically recover the embedded clock signal and
retime the data from SMPTE 292M compliant digital video
signals. There is also a selectable reclocked serial data
output and the ability to bypass the reclocker stage.
A unique feature, Input Jitter Indicator (IJI), is included for
robust system design. This feature is used to indicate
excessive input jitter before the chip mutes the outputs.
The Serial to Parallel conversion stage provides 1:20 S/P
conversion
The GS1545 uses the GO1515 external VCO connected to
the internal PLL circuitry to achieve ultra low noise PLL
performance.
ORDERING INFORMATION
PART NUMBER
PACKAGE
GS1545-CQR
128 pin MQFP
TEMPERATURE
0°C to 70°C
SDOint
SDI
SDI
EQUALIZER
CORE
SDOint ANALOG-
DIGITAL
MUX &
RECLOCKER
CORE
BUFFER
S/P CONVERTER
BUFFER2
DDI DDI_VTT DDI
(opt)
A/D SDO_EN
SIMPLIFIED BLOCK DIAGRAM
DATA_OUT[19:0]
PCLK_OUT
SDO
SDO
Revision Date: August 2000
Document No. 522 - 28 - 00
GENNUM CORPORATION P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3
Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946 E-mail: [email protected]
www.gennum.com
1 page  
AC ELECTRICAL CHARACTERISTICS - EQUALIZER STAGE
VCC = 5V, TA = 0°C to 70°C unless otherwise shown.
PARAMETER
CONDITIONS
SYMBOL
Equalization
Input Resistance (SDI, SDI)
Input Capacitance (SDI, SDI)
Belden 1694A
CIN
MIN
TYP
MAX
UNITS
TEST
LEVEL
- 110 - m 2
- 2.8 - kΩ 7
- 2.0 - pF 7
AC ELECTRICAL CHARACTERISTICS - SERIAL TO PARALLEL STAGE
VCC = 5V, TA = 0°C to 70°C unless otherwise shown.
PARAMETER
CONDITIONS
SYMBOL
MIN TYP
Parallel Output Clock Frequency
Clock Pulse Width Low
Clock Pulse Width High
Output signal Rise/Fall time
Output Signal Rise/Fall Time Matching
Output Setup Time
Output Hold Time
SMPTE 292M
15pF load
15pF load
15pF load
15pF load
15pF load
15pF load
PCLK_OUT
tPWL
tPWH
tr, tf
trfm
tOD
tOH
74.25/1.001
5
5
-
-
4
5
74.25
7
6
2000
1000
6
7
MAX
-
-
-
4000
2000
-
-
UNITS
TEST
LEVEL
MHz
1
ns 7
ns 7
ps 7
ps 7
ns 2
ns 2
TEST LEVELS
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges.
2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using
correlated test.
3. Production test at room temperature and nominal supply voltage.
4. QA sample test.
5. Calculated result based on Level 1,2, or 3.
6. Not tested. Guaranteed by design simulations.
7. Not tested. Based on characterization of nominal parts.
8. Not tested. Based on existing design/characterization data of similar product.
GENNUM CORPORATION
5
522 - 28 - 00
5 Page 
10k 5k
LFA_VCC
LFS
100µA
100µA
100µA
100µA
Fig. 7 LFS Input Circuit
LFA_VEE
PD_VCC
10k
PLL_LOCK
PD_VEE
Fig. 8 PLL_LOCK Output Circuit
PD_VCC
10k
IJI
5k
VCC
30k
A
PD_VEE
Fig. 9 IJI Output Circuit
20k
A/D
PD_VCC
16k
+
-
2.4V
100µA
PD_VEE
Fig. 10 A/D Input Circuit
GENNUM CORPORATION
11
PD_VCC
16k
BYPASS
+
-
V = 2.4V
100µA
PD_VEE
Fig. 11 BYPASS Circuit
LFA_VCC
20k
LBCONT
5k
LFA_VEE
Fig. 12 LBCONT Circuit
SP_VCC
100
D[19:0]
27k
SP_VEE
Fig. 13 D[19:0] Output Circuit
PCLK_VCC
100
PCLK
27k
PCLK_VEE
Fig. 14 PCLK Output Circuit
522 - 28 - 00
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet GS1545.PDF ] | |
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